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https://github.com/brain-hackers/u-boot-brain
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c9056653ec
The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
118 lines
1.9 KiB
C
118 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <common.h>
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void flush_dcache_all(void)
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{
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/*
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* Andes' AX25 does not have a coherence agent. U-Boot must use data
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* cache flush and invalidate functions to keep data in the system
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* coherent.
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* The implementation of the fence instruction in the AX25 flushes the
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* data cache and is used for this purpose.
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*/
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asm volatile ("fence" ::: "memory");
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void icache_enable(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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#ifdef CONFIG_RISCV_NDS_CACHE
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"ori t0, t1, 0x1\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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}
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void icache_disable(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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#ifdef CONFIG_RISCV_NDS_CACHE
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asm volatile (
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"fence.i\n\t"
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"csrr t1, mcache_ctl\n\t"
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"andi t0, t1, ~0x1\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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}
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void dcache_enable(void)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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#ifdef CONFIG_RISCV_NDS_CACHE
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"ori t0, t1, 0x2\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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}
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void dcache_disable(void)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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#ifdef CONFIG_RISCV_NDS_CACHE
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asm volatile (
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"fence\n\t"
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"csrr t1, mcache_ctl\n\t"
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"andi t0, t1, ~0x2\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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}
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int icache_status(void)
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{
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int ret = 0;
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#ifdef CONFIG_RISCV_NDS_CACHE
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"andi %0, t1, 0x01\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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#endif
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return ret;
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}
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int dcache_status(void)
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{
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int ret = 0;
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#ifdef CONFIG_RISCV_NDS_CACHE
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"andi %0, t1, 0x02\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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#endif
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return ret;
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}
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