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52923c6db7
AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
8 lines
184 B
Makefile
8 lines
184 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2017 Andes Technology Corporation
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# Rick Chen, Andes Technology Corporation <rick@andestech.com>
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obj-y := cpu.o
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obj-y += cache.o
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