Simon Glass aff2523f69 x86: Add support for MTRRs ... Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>		2015-01-13 07:25:00 -08:00
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car.S	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
coreboot.c	x86: Add support for MTRRs	2015-01-13 07:25:00 -08:00
ipchecksum.c	Replace <compiler.h> with <linux/compiler.h>	2014-12-08 09:35:46 -05:00
Makefile	x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory	2014-11-23 06:49:02 -05:00
pci.c	Merge git://git.denx.de/u-boot-x86	2014-11-24 12:00:00 -05:00
sdram.c	Merge git://git.denx.de/u-boot-x86	2014-11-24 12:00:00 -05:00
tables.c	x86: Tidy up coreboot header usage	2014-11-21 07:34:13 +01:00
timestamp.c	x86: Support adding coreboot timestanps to bootstage	2013-05-13 13:33:22 -07:00