Simon Glass aff2523f69 x86: Add support for MTRRs ... Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>		2015-01-13 07:25:00 -08:00
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cpu	x86: Add support for MTRRs	2015-01-13 07:25:00 -08:00
dts	x86: crownbay: Add pci devices in the dts file	2015-01-13 07:24:57 -08:00
include/asm	x86: Add support for MTRRs	2015-01-13 07:25:00 -08:00
lib	x86: Tidy up VESA mode numbers	2015-01-13 07:24:59 -08:00
config.mk	x86: Remove REALMODE_BASE which is no longer used	2014-11-21 07:24:08 +01:00
Kconfig	x86: Drop RAMTOP Kconfig	2015-01-13 07:24:58 -08:00
Makefile	Kbuild: introduce Makefile in arch/$ARCH/	2014-12-08 09:35:45 -05:00