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![Michal Simek](/assets/img/avatar_default.png)
Map all resource for R5 to operate properly.
The patch is done based on the commit 23f7b1a776
("armv7R: K3: am654:
Enable MPU regions") which also map the whole 4GB at first and then change
mapping for DDR.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
37 lines
655 B
C
37 lines
655 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <asm/armv7_mpu.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct mpu_region_config region_config[] = {
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{ 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
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SHARED_WRITE_BUFFERED, REGION_4GB },
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{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
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O_I_WB_RD_WR_ALLOC, REGION_1GB },
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};
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int arch_cpu_init(void)
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{
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gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
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setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
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return 0;
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}
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/*
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* Perform the low-level reset.
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*/
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void reset_cpu(ulong addr)
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{
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while (1)
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;
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}
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