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xilinx: r5: Fix MPU setting for R5
Map all resource for R5 to operate properly.
The patch is done based on the commit 23f7b1a776
("armv7R: K3: am654:
Enable MPU regions") which also map the whole 4GB at first and then change
mapping for DDR.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
parent
b76907ef90
commit
e3259a700a
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@ -11,11 +11,9 @@
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DECLARE_GLOBAL_DATA_PTR;
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struct mpu_region_config region_config[] = {
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{ 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW,
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O_I_WB_RD_WR_ALLOC, REGION_1GB },
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{ 0x20000000, REGION_1, XN_EN, PRIV_RO_USR_RO,
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O_I_WB_RD_WR_ALLOC, REGION_512MB },
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{ 0x40000000, REGION_2, XN_EN, PRIV_RO_USR_RO,
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{ 0x00000000, REGION_0, XN_EN, PRIV_RW_USR_RW,
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SHARED_WRITE_BUFFERED, REGION_4GB },
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{ 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW,
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O_I_WB_RD_WR_ALLOC, REGION_1GB },
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};
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@ -23,8 +21,7 @@ int arch_cpu_init(void)
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{
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gd->cpu_clk = CONFIG_CPU_FREQ_HZ;
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setup_mpu_regions(region_config, sizeof(region_config) /
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sizeof(struct mpu_region_config));
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setup_mpu_regions(region_config, ARRAY_SIZE(region_config));
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return 0;
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}
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