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https://github.com/brain-hackers/u-boot-brain
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aacdd79095
This patch intends to remove all code which enables hardware read leveling. All characterization environments may not cope up with h/w read leveling enabled, so we must disable this. Also, disabling h/w read leveling improves the MIF LVcc value (LVcc value is the value at which DDR will fail to work properly). Improving LVcc means we have enough voltage margin for MIF. When h/w leveling is enabled, we have almost zero volatge margin. Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> |
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| .. | ||
| clock_init_exynos4.c | ||
| clock_init_exynos5.c | ||
| clock_init.h | ||
| clock.c | ||
| common_setup.h | ||
| config.mk | ||
| dmc_common.c | ||
| dmc_init_ddr3.c | ||
| dmc_init_exynos4.c | ||
| exynos4_setup.h | ||
| exynos5_setup.h | ||
| lowlevel_init.c | ||
| Makefile | ||
| pinmux.c | ||
| power.c | ||
| soc.c | ||
| spl_boot.c | ||
| system.c | ||
| tzpc.c | ||