u-boot-brain/arch/riscv/cpu
Bin Meng 4d2583dba1 riscv: Access CSRs using CSR numbers
We should prefer accessing CSRs using their CSR numbers
because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR
   numbers as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not
   recognize newly added CSRs by name.

This commit is inspired from Linux kernel commit a3182c91ef4e
("RISC-V: Access CSRs using CSR numbers").

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
2019-08-15 13:42:28 +08:00
..
ax25 CONFIG_SPL_SYS_[DI]CACHE_OFF: add 2019-05-18 08:15:35 -04:00
generic riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems 2019-02-27 09:12:33 +08:00
cpu.c riscv: Access CSRs using CSR numbers 2019-08-15 13:42:28 +08:00
Makefile riscv: Move trap handler codes to mtrap.S 2018-12-18 09:56:27 +08:00
mtrap.S riscv: Return to previous privilege level after trap handling 2018-12-18 09:56:27 +08:00
start.S riscv: Access CSRs using CSR numbers 2019-08-15 13:42:28 +08:00
u-boot.lds riscv: Make start.S available for all targets 2018-10-03 17:48:14 +08:00