mirror of
https://github.com/brain-hackers/u-boot-brain
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96fa1e4385
Convert altera_tse to driver model and phylib. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
258 lines
8.4 KiB
C
258 lines
8.4 KiB
C
/*
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* Altera 10/100/1000 triple speed ethernet mac
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*
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* Copyright (C) 2008 Altera Corporation.
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* Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ALTERA_TSE_H_
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#define _ALTERA_TSE_H_
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#define __packed_1_ __attribute__ ((packed, aligned(1)))
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/* SGDMA Stuff */
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#define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001)
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#define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002)
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#define ALT_SGDMA_STATUS_DESC_COMPLETED_MSK (0x00000004)
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#define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008)
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#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010)
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#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020)
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#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040)
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#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000)
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#define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \
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| ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \
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| ALT_SGDMA_CONTROL_IE_GLOBAL_MSK)
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/*
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* Descriptor control bit masks & offsets
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*
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* Note: The control byte physically occupies bits [31:24] in memory.
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* The following bit-offsets are expressed relative to the LSB of
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* the control register bitfield.
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*/
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK (0x00000001)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK (0x00000002)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK (0x00000004)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_ATLANTIC_CHANNEL_MSK (0x00000008)
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#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK (0x00000080)
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/*
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* Descriptor status bit masks & offsets
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*
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* Note: The status byte physically occupies bits [23:16] in memory.
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* The following bit-offsets are expressed relative to the LSB of
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* the status register bitfield.
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*/
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_CRC_MSK (0x00000001)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_PARITY_MSK (0x00000002)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_OVERFLOW_MSK (0x00000004)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_SYNC_MSK (0x00000008)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_UEOP_MSK (0x00000010)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MEOP_MSK (0x00000020)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_E_MSOP_MSK (0x00000040)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK (0x00000080)
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#define ALT_SGDMA_DESCRIPTOR_STATUS_ERROR_MSK (0x0000007F)
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/*
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* The SGDMA controller buffer descriptor allocates
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* 64 bits for each address. To support ANSI C, the
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* struct implementing a descriptor places 32-bits
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* of padding directly above each address; each pad must
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* be cleared when initializing a descriptor.
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*/
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/*
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* Buffer Descriptor data structure
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*
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*/
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struct alt_sgdma_descriptor {
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unsigned int source; /* the address of data to be read. */
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unsigned int source_pad;
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unsigned int destination; /* the address to write data */
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unsigned int destination_pad;
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unsigned int next; /* the next descriptor in the list. */
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unsigned int next_pad;
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unsigned short bytes_to_transfer; /* the number of bytes to transfer */
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unsigned char read_burst;
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unsigned char write_burst;
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unsigned short actual_bytes_transferred;/* bytes transferred by DMA */
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unsigned char descriptor_status;
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unsigned char descriptor_control;
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} __packed_1_;
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/* SG-DMA Control/Status Slave registers map */
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struct alt_sgdma_registers {
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unsigned int status;
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unsigned int status_pad[3];
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unsigned int control;
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unsigned int control_pad[3];
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unsigned int next_descriptor_pointer;
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unsigned int descriptor_pad[3];
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};
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/* TSE Stuff */
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#define ALTERA_TSE_CMD_TX_ENA_MSK (0x00000001)
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#define ALTERA_TSE_CMD_RX_ENA_MSK (0x00000002)
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#define ALTERA_TSE_CMD_XON_GEN_MSK (0x00000004)
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#define ALTERA_TSE_CMD_ETH_SPEED_MSK (0x00000008)
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#define ALTERA_TSE_CMD_PROMIS_EN_MSK (0x00000010)
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#define ALTERA_TSE_CMD_PAD_EN_MSK (0x00000020)
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#define ALTERA_TSE_CMD_CRC_FWD_MSK (0x00000040)
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#define ALTERA_TSE_CMD_PAUSE_FWD_MSK (0x00000080)
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#define ALTERA_TSE_CMD_PAUSE_IGNORE_MSK (0x00000100)
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#define ALTERA_TSE_CMD_TX_ADDR_INS_MSK (0x00000200)
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#define ALTERA_TSE_CMD_HD_ENA_MSK (0x00000400)
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#define ALTERA_TSE_CMD_EXCESS_COL_MSK (0x00000800)
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#define ALTERA_TSE_CMD_LATE_COL_MSK (0x00001000)
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#define ALTERA_TSE_CMD_SW_RESET_MSK (0x00002000)
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#define ALTERA_TSE_CMD_MHASH_SEL_MSK (0x00004000)
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#define ALTERA_TSE_CMD_LOOPBACK_MSK (0x00008000)
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/* Bits (18:16) = address select */
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#define ALTERA_TSE_CMD_TX_ADDR_SEL_MSK (0x00070000)
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#define ALTERA_TSE_CMD_MAGIC_ENA_MSK (0x00080000)
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#define ALTERA_TSE_CMD_SLEEP_MSK (0x00100000)
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#define ALTERA_TSE_CMD_WAKEUP_MSK (0x00200000)
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#define ALTERA_TSE_CMD_XOFF_GEN_MSK (0x00400000)
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#define ALTERA_TSE_CMD_CNTL_FRM_ENA_MSK (0x00800000)
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#define ALTERA_TSE_CMD_NO_LENGTH_CHECK_MSK (0x01000000)
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#define ALTERA_TSE_CMD_ENA_10_MSK (0x02000000)
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#define ALTERA_TSE_CMD_RX_ERR_DISC_MSK (0x04000000)
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/* Bits (30..27) reserved */
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#define ALTERA_TSE_CMD_CNT_RESET_MSK (0x80000000)
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#define ALTERA_TSE_TX_CMD_STAT_TX_SHIFT16 (0x00040000)
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#define ALTERA_TSE_TX_CMD_STAT_OMIT_CRC (0x00020000)
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#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000)
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#define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
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/* MAC register Space */
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struct alt_tse_mac {
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unsigned int megacore_revision;
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unsigned int scratch_pad;
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unsigned int command_config;
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unsigned int mac_addr_0;
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unsigned int mac_addr_1;
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unsigned int max_frame_length;
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unsigned int pause_quanta;
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unsigned int rx_sel_empty_threshold;
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unsigned int rx_sel_full_threshold;
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unsigned int tx_sel_empty_threshold;
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unsigned int tx_sel_full_threshold;
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unsigned int rx_almost_empty_threshold;
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unsigned int rx_almost_full_threshold;
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unsigned int tx_almost_empty_threshold;
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unsigned int tx_almost_full_threshold;
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unsigned int mdio_phy0_addr;
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unsigned int mdio_phy1_addr;
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/* only if 100/1000 BaseX PCS, reserved otherwise */
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unsigned int reservedx44[5];
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unsigned int reg_read_access_status;
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unsigned int min_tx_ipg_length;
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/* IEEE 802.3 oEntity Managed Object Support */
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unsigned int aMACID_1; /*The MAC addresses */
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unsigned int aMACID_2;
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unsigned int aFramesTransmittedOK;
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unsigned int aFramesReceivedOK;
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unsigned int aFramesCheckSequenceErrors;
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unsigned int aAlignmentErrors;
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unsigned int aOctetsTransmittedOK;
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unsigned int aOctetsReceivedOK;
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/* IEEE 802.3 oPausedEntity Managed Object Support */
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unsigned int aTxPAUSEMACCtrlFrames;
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unsigned int aRxPAUSEMACCtrlFrames;
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/* IETF MIB (MIB-II) Object Support */
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unsigned int ifInErrors;
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unsigned int ifOutErrors;
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unsigned int ifInUcastPkts;
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unsigned int ifInMulticastPkts;
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unsigned int ifInBroadcastPkts;
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unsigned int ifOutDiscards;
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unsigned int ifOutUcastPkts;
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unsigned int ifOutMulticastPkts;
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unsigned int ifOutBroadcastPkts;
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/* IETF RMON MIB Object Support */
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unsigned int etherStatsDropEvent;
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unsigned int etherStatsOctets;
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unsigned int etherStatsPkts;
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unsigned int etherStatsUndersizePkts;
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unsigned int etherStatsOversizePkts;
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unsigned int etherStatsPkts64Octets;
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unsigned int etherStatsPkts65to127Octets;
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unsigned int etherStatsPkts128to255Octets;
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unsigned int etherStatsPkts256to511Octets;
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unsigned int etherStatsPkts512to1023Octets;
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unsigned int etherStatsPkts1024to1518Octets;
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unsigned int etherStatsPkts1519toXOctets;
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unsigned int etherStatsJabbers;
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unsigned int etherStatsFragments;
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unsigned int reservedxE4;
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/*FIFO control register. */
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unsigned int tx_cmd_stat;
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unsigned int rx_cmd_stat;
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unsigned int ipaccTxConf;
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unsigned int ipaccRxConf;
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unsigned int ipaccRxStat;
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unsigned int ipaccRxStatSum;
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/*Multicast address resolution table */
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unsigned int hash_table[64];
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/*Registers 0 to 31 within PHY device 0/1 */
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unsigned int mdio_phy0[0x20];
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unsigned int mdio_phy1[0x20];
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/*4 Supplemental MAC Addresses */
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unsigned int supp_mac_addr_0_0;
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unsigned int supp_mac_addr_0_1;
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unsigned int supp_mac_addr_1_0;
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unsigned int supp_mac_addr_1_1;
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unsigned int supp_mac_addr_2_0;
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unsigned int supp_mac_addr_2_1;
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unsigned int supp_mac_addr_3_0;
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unsigned int supp_mac_addr_3_1;
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unsigned int reservedx320[56];
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};
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struct altera_tse_priv {
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struct alt_tse_mac *mac_dev;
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struct alt_sgdma_registers *sgdma_rx;
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struct alt_sgdma_registers *sgdma_tx;
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unsigned int rx_fifo_depth;
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unsigned int tx_fifo_depth;
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struct alt_sgdma_descriptor *rx_desc;
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struct alt_sgdma_descriptor *tx_desc;
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unsigned char *rx_buf;
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unsigned int phyaddr;
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unsigned int interface;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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#endif /* _ALTERA_TSE_H_ */
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