net: convert altera_tse to driver model and phylib
Convert altera_tse to driver model and phylib. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Thomas Chou
parent
8a3ea97966
commit
96fa1e4385
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@ -18,6 +18,8 @@ CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_ALTERA_PIO=y
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CONFIG_MISC=y
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CONFIG_ALTERA_SYSID=y
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CONFIG_DM_ETH=y
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CONFIG_ALTERA_TSE=y
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CONFIG_ALTERA_JTAG_UART=y
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CONFIG_ALTERA_JTAG_UART_BYPASS=y
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CONFIG_TIMER=y
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@ -0,0 +1,112 @@
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* Altera Triple-Speed Ethernet MAC driver (TSE)
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Required properties:
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- compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
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be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
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- reg: Address and length of the register set for the device. It contains
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the information of registers in the same order as described by reg-names
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- reg-names: Should contain the reg names
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"control_port": MAC configuration space region
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"tx_csr": xDMA Tx dispatcher control and status space region
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"tx_desc": MSGDMA Tx dispatcher descriptor space region
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"rx_csr" : xDMA Rx dispatcher control and status space region
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"rx_desc": MSGDMA Rx dispatcher descriptor space region
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"rx_resp": MSGDMA Rx dispatcher response space region
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"s1": SGDMA descriptor memory
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- interrupts: Should contain the TSE interrupts and it's mode.
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- interrupt-names: Should contain the interrupt names
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"rx_irq": xDMA Rx dispatcher interrupt
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"tx_irq": xDMA Tx dispatcher interrupt
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- rx-fifo-depth: MAC receive FIFO buffer depth in bytes
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- tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
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- phy-mode: See ethernet.txt in the same directory.
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- phy-handle: See ethernet.txt in the same directory.
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- phy-addr: See ethernet.txt in the same directory. A configuration should
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include phy-handle or phy-addr.
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- altr,has-supplementary-unicast:
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If present, TSE supports additional unicast addresses.
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Otherwise additional unicast addresses are not supported.
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- altr,has-hash-multicast-filter:
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If present, TSE supports a hash based multicast filter.
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Otherwise, hash-based multicast filtering is not supported.
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- mdio device tree subnode: When the TSE has a phy connected to its local
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mdio, there must be device tree subnode with the following
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required properties:
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- compatible: Must be "altr,tse-mdio".
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- #address-cells: Must be <1>.
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- #size-cells: Must be <0>.
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For each phy on the mdio bus, there must be a node with the following
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fields:
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- reg: phy id used to communicate to phy.
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- device_type: Must be "ethernet-phy".
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Optional properties:
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- local-mac-address: See ethernet.txt in the same directory.
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- max-frame-size: See ethernet.txt in the same directory.
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Example:
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tse_sub_0_eth_tse_0: ethernet@0x1,00000000 {
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compatible = "altr,tse-msgdma-1.0";
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reg = <0x00000001 0x00000000 0x00000400>,
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<0x00000001 0x00000460 0x00000020>,
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<0x00000001 0x00000480 0x00000020>,
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<0x00000001 0x000004A0 0x00000008>,
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<0x00000001 0x00000400 0x00000020>,
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<0x00000001 0x00000420 0x00000020>;
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reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
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interrupt-parent = <&hps_0_arm_gic_0>;
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interrupts = <0 41 4>, <0 40 4>;
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interrupt-names = "rx_irq", "tx_irq";
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rx-fifo-depth = <2048>;
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tx-fifo-depth = <2048>;
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address-bits = <48>;
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max-frame-size = <1500>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-mode = "gmii";
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altr,has-supplementary-unicast;
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altr,has-hash-multicast-filter;
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phy-handle = <&phy0>;
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mdio {
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compatible = "altr,tse-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0x0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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reg = <0x1>;
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device_type = "ethernet-phy";
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};
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};
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};
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tse_sub_1_eth_tse_0: ethernet@0x1,00001000 {
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compatible = "altr,tse-msgdma-1.0";
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reg = <0x00000001 0x00001000 0x00000400>,
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<0x00000001 0x00001460 0x00000020>,
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<0x00000001 0x00001480 0x00000020>,
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<0x00000001 0x000014A0 0x00000008>,
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<0x00000001 0x00001400 0x00000020>,
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<0x00000001 0x00001420 0x00000020>;
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reg-names = "control_port", "rx_csr", "rx_desc", "rx_resp", "tx_csr", "tx_desc";
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interrupt-parent = <&hps_0_arm_gic_0>;
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interrupts = <0 43 4>, <0 42 4>;
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interrupt-names = "rx_irq", "tx_irq";
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rx-fifo-depth = <2048>;
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tx-fifo-depth = <2048>;
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address-bits = <48>;
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max-frame-size = <1500>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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phy-mode = "gmii";
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altr,has-supplementary-unicast;
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altr,has-hash-multicast-filter;
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phy-handle = <&phy1>;
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};
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@ -25,6 +25,15 @@ menuconfig NETDEVICES
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if NETDEVICES
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config ALTERA_TSE
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bool "Altera Triple-Speed Ethernet MAC support"
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depends on DM_ETH
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select PHYLIB
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help
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This driver supports the Altera Triple-Speed (TSE) Ethernet MAC.
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Please find details on the "Triple-Speed Ethernet MegaCore Function
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Resource Center" of Altera.
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config E1000
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bool "Intel PRO/1000 Gigabit Ethernet support"
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help
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File diff suppressed because it is too large
Load Diff
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@ -13,102 +13,6 @@
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#define __packed_1_ __attribute__ ((packed, aligned(1)))
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/* PHY Stuff */
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#define miim_end -2
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#define miim_read -1
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#define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
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#ifndef CONFIG_SYS_TBIPA_VALUE
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#define CONFIG_SYS_TBIPA_VALUE 0x1f
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#endif
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#define MIIMCFG_INIT_VALUE 0x00000003
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#define MIIMCFG_RESET 0x80000000
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#define MIIMIND_BUSY 0x00000001
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#define MIIMIND_NOTVALID 0x00000004
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#define MIIM_CONTROL 0x00
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#define MIIM_CONTROL_RESET 0x00009140
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#define MIIM_CONTROL_INIT 0x00001140
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#define MIIM_CONTROL_RESTART 0x00001340
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#define MIIM_ANEN 0x00001000
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#define MIIM_CR 0x00
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#define MIIM_CR_RST 0x00008000
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#define MIIM_CR_INIT 0x00001000
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#define MIIM_STATUS 0x1
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#define MIIM_STATUS_AN_DONE 0x00000020
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#define MIIM_STATUS_LINK 0x0004
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#define MIIM_PHYIR1 0x2
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#define MIIM_PHYIR2 0x3
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#define MIIM_ANAR 0x4
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#define MIIM_ANAR_INIT 0x1e1
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#define MIIM_TBI_ANLPBPA 0x5
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#define MIIM_TBI_ANLPBPA_HALF 0x00000040
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#define MIIM_TBI_ANLPBPA_FULL 0x00000020
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#define MIIM_TBI_ANEX 0x6
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#define MIIM_TBI_ANEX_NP 0x00000004
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#define MIIM_TBI_ANEX_PRX 0x00000002
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#define MIIM_GBIT_CONTROL 0x9
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#define MIIM_GBIT_CONTROL_INIT 0xe00
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#define MIIM_EXT_PAGE_ACCESS 0x1f
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/* 88E1011 PHY Status Register */
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#define MIIM_88E1011_PHY_STATUS 0x11
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#define MIIM_88E1011_PHYSTAT_SPEED 0xc000
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#define MIIM_88E1011_PHYSTAT_GBIT 0x8000
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#define MIIM_88E1011_PHYSTAT_100 0x4000
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#define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
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#define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
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#define MIIM_88E1011_PHYSTAT_LINK 0x0400
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#define MIIM_88E1011_PHY_SCR 0x10
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#define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
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#define MIIM_88E1111_PHY_EXT_CR 0x14
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#define MIIM_88E1111_PHY_EXT_SR 0x1b
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/* 88E1111 PHY LED Control Register */
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#define MIIM_88E1111_PHY_LED_CONTROL 24
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#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
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#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
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#define MIIM_READ_COMMAND 0x00000001
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/* struct phy_info: a structure which defines attributes for a PHY
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* id will contain a number which represents the PHY. During
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* startup, the driver will poll the PHY to find out what its
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* UID--as defined by registers 2 and 3--is. The 32-bit result
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* gotten from the PHY will be shifted right by "shift" bits to
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* discard any bits which may change based on revision numbers
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* unimportant to functionality
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*
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* The struct phy_cmd entries represent pointers to an arrays of
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* commands which tell the driver what to do to the PHY.
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*/
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struct phy_info {
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uint id;
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char *name;
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uint shift;
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/* Called to configure the PHY, and modify the controller
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* based on the results */
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struct phy_cmd *config;
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/* Called when starting up the controller */
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struct phy_cmd *startup;
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/* Called when bringing down the controller */
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struct phy_cmd *shutdown;
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};
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/* SGDMA Stuff */
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#define ALT_SGDMA_STATUS_ERROR_MSK (0x00000001)
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#define ALT_SGDMA_STATUS_EOP_ENCOUNTERED_MSK (0x00000002)
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@ -116,18 +20,9 @@ struct phy_info {
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#define ALT_SGDMA_STATUS_CHAIN_COMPLETED_MSK (0x00000008)
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#define ALT_SGDMA_STATUS_BUSY_MSK (0x00000010)
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#define ALT_SGDMA_CONTROL_IE_ERROR_MSK (0x00000001)
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#define ALT_SGDMA_CONTROL_IE_EOP_ENCOUNTERED_MSK (0x00000002)
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#define ALT_SGDMA_CONTROL_IE_DESC_COMPLETED_MSK (0x00000004)
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#define ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK (0x00000008)
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#define ALT_SGDMA_CONTROL_IE_GLOBAL_MSK (0x00000010)
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#define ALT_SGDMA_CONTROL_RUN_MSK (0x00000020)
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#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK (0x00000040)
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#define ALT_SGDMA_CONTROL_IE_MAX_DESC_PROCESSED_MSK (0x00000080)
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#define ALT_SGDMA_CONTROL_MAX_DESC_PROCESSED_MSK (0x0000FF00)
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#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK (0x00010000)
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#define ALT_SGDMA_CONTROL_PARK_MSK (0x00020000)
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#define ALT_SGDMA_CONTROL_CLEAR_INTERRUPT_MSK (0x80000000)
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#define ALTERA_TSE_SGDMA_INTR_MASK (ALT_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK \
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| ALT_SGDMA_STATUS_DESC_COMPLETED_MSK \
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@ -176,13 +71,13 @@ struct phy_info {
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*
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*/
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struct alt_sgdma_descriptor {
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unsigned int *source; /* the address of data to be read. */
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unsigned int source; /* the address of data to be read. */
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unsigned int source_pad;
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unsigned int *destination; /* the address to write data */
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unsigned int destination; /* the address to write data */
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unsigned int destination_pad;
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unsigned int *next; /* the next descriptor in the list. */
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unsigned int next; /* the next descriptor in the list. */
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unsigned int next_pad;
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unsigned short bytes_to_transfer; /* the number of bytes to transfer */
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@ -241,112 +136,15 @@ struct alt_sgdma_registers {
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#define ALTERA_TSE_RX_CMD_STAT_RX_SHIFT16 (0x02000000)
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#define ALT_TSE_SW_RESET_WATCHDOG_CNTR 10000
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#define ALT_TSE_SGDMA_BUSY_WATCHDOG_CNTR 90000000
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/* Command_Config Register Bit Definitions */
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typedef volatile union __alt_tse_command_config {
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unsigned int image;
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struct {
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unsigned int
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transmit_enable:1, /* bit 0 */
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receive_enable:1, /* bit 1 */
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pause_frame_xon_gen:1, /* bit 2 */
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ethernet_speed:1, /* bit 3 */
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promiscuous_enable:1, /* bit 4 */
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pad_enable:1, /* bit 5 */
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crc_forward:1, /* bit 6 */
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pause_frame_forward:1, /* bit 7 */
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pause_frame_ignore:1, /* bit 8 */
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set_mac_address_on_tx:1, /* bit 9 */
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halfduplex_enable:1, /* bit 10 */
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excessive_collision:1, /* bit 11 */
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late_collision:1, /* bit 12 */
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software_reset:1, /* bit 13 */
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multicast_hash_mode_sel:1, /* bit 14 */
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loopback_enable:1, /* bit 15 */
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src_mac_addr_sel_on_tx:3, /* bit 18:16 */
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magic_packet_detect:1, /* bit 19 */
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sleep_mode_enable:1, /* bit 20 */
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wake_up_request:1, /* bit 21 */
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pause_frame_xoff_gen:1, /* bit 22 */
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control_frame_enable:1, /* bit 23 */
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payload_len_chk_disable:1, /* bit 24 */
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enable_10mbps_intf:1, /* bit 25 */
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rx_error_discard_enable:1, /* bit 26 */
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reserved_bits:4, /* bit 30:27 */
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self_clear_counter_reset:1; /* bit 31 */
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} __packed_1_ bits;
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} __packed_1_ alt_tse_command_config;
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/* Tx_Cmd_Stat Register Bit Definitions */
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typedef volatile union __alt_tse_tx_cmd_stat {
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unsigned int image;
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struct {
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unsigned int reserved_lsbs:17, /* bit 16:0 */
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omit_crc:1, /* bit 17 */
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tx_shift16:1, /* bit 18 */
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reserved_msbs:13; /* bit 31:19 */
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} __packed_1_ bits;
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} alt_tse_tx_cmd_stat;
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/* Rx_Cmd_Stat Register Bit Definitions */
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typedef volatile union __alt_tse_rx_cmd_stat {
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unsigned int image;
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struct {
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unsigned int reserved_lsbs:25, /* bit 24:0 */
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rx_shift16:1, /* bit 25 */
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reserved_msbs:6; /* bit 31:26 */
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} __packed_1_ bits;
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} alt_tse_rx_cmd_stat;
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struct alt_tse_mdio {
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unsigned int control; /*PHY device operation control register */
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unsigned int status; /*PHY device operation status register */
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unsigned int phy_id1; /*Bits 31:16 of PHY identifier. */
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unsigned int phy_id2; /*Bits 15:0 of PHY identifier. */
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unsigned int auto_negotiation_advertisement;
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unsigned int remote_partner_base_page_ability;
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unsigned int reg6;
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unsigned int reg7;
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unsigned int reg8;
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unsigned int reg9;
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unsigned int rega;
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unsigned int regb;
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unsigned int regc;
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unsigned int regd;
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unsigned int rege;
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unsigned int regf;
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unsigned int reg10;
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unsigned int reg11;
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unsigned int reg12;
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unsigned int reg13;
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unsigned int reg14;
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unsigned int reg15;
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unsigned int reg16;
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unsigned int reg17;
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unsigned int reg18;
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unsigned int reg19;
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unsigned int reg1a;
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unsigned int reg1b;
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unsigned int reg1c;
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unsigned int reg1d;
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unsigned int reg1e;
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unsigned int reg1f;
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};
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#define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
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/* MAC register Space */
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struct alt_tse_mac {
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unsigned int megacore_revision;
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unsigned int scratch_pad;
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alt_tse_command_config command_config;
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unsigned int command_config;
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unsigned int mac_addr_0;
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unsigned int mac_addr_1;
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unsigned int max_frame_length;
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@ -413,8 +211,8 @@ struct alt_tse_mac {
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unsigned int reservedxE4;
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/*FIFO control register. */
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alt_tse_tx_cmd_stat tx_cmd_stat;
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alt_tse_rx_cmd_stat rx_cmd_stat;
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unsigned int tx_cmd_stat;
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unsigned int rx_cmd_stat;
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unsigned int ipaccTxConf;
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unsigned int ipaccRxConf;
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@ -425,8 +223,8 @@ struct alt_tse_mac {
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unsigned int hash_table[64];
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/*Registers 0 to 31 within PHY device 0/1 */
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struct alt_tse_mdio mdio_phy0;
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struct alt_tse_mdio mdio_phy1;
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unsigned int mdio_phy0[0x20];
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unsigned int mdio_phy1[0x20];
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/*4 Supplemental MAC Addresses */
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unsigned int supp_mac_addr_0_0;
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@ -441,52 +239,19 @@ struct alt_tse_mac {
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unsigned int reservedx320[56];
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};
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/* flags: TSE MII modes */
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||||
/* GMII/MII = 0 */
|
||||
/* RGMII = 1 */
|
||||
/* RGMII_ID = 2 */
|
||||
/* RGMII_TXID = 3 */
|
||||
/* RGMII_RXID = 4 */
|
||||
/* SGMII = 5 */
|
||||
struct altera_tse_priv {
|
||||
char devname[16];
|
||||
volatile struct alt_tse_mac *mac_dev;
|
||||
volatile struct alt_sgdma_registers *sgdma_rx;
|
||||
volatile struct alt_sgdma_registers *sgdma_tx;
|
||||
unsigned int rx_sgdma_irq;
|
||||
unsigned int tx_sgdma_irq;
|
||||
unsigned int has_descriptor_mem;
|
||||
unsigned int descriptor_mem_base;
|
||||
unsigned int descriptor_mem_size;
|
||||
volatile struct alt_sgdma_descriptor *rx_desc;
|
||||
volatile struct alt_sgdma_descriptor *tx_desc;
|
||||
volatile unsigned char *rx_buf;
|
||||
struct phy_info *phyinfo;
|
||||
struct alt_tse_mac *mac_dev;
|
||||
struct alt_sgdma_registers *sgdma_rx;
|
||||
struct alt_sgdma_registers *sgdma_tx;
|
||||
unsigned int rx_fifo_depth;
|
||||
unsigned int tx_fifo_depth;
|
||||
struct alt_sgdma_descriptor *rx_desc;
|
||||
struct alt_sgdma_descriptor *tx_desc;
|
||||
unsigned char *rx_buf;
|
||||
unsigned int phyaddr;
|
||||
unsigned int flags;
|
||||
unsigned int link;
|
||||
unsigned int duplexity;
|
||||
unsigned int speed;
|
||||
unsigned int interface;
|
||||
struct phy_device *phydev;
|
||||
struct mii_dev *bus;
|
||||
};
|
||||
|
||||
/* Phy stuff continued */
|
||||
/*
|
||||
* struct phy_cmd: A command for reading or writing a PHY register
|
||||
*
|
||||
* mii_reg: The register to read or write
|
||||
*
|
||||
* mii_data: For writes, the value to put in the register.
|
||||
* A value of -1 indicates this is a read.
|
||||
*
|
||||
* funct: A function pointer which is invoked for each command.
|
||||
* For reads, this function will be passed the value read
|
||||
* from the PHY, and process it.
|
||||
* For writes, the result of this function will be written
|
||||
* to the PHY register
|
||||
*/
|
||||
struct phy_cmd {
|
||||
uint mii_reg;
|
||||
uint mii_data;
|
||||
uint(*funct) (uint mii_reg, struct altera_tse_priv *priv);
|
||||
};
|
||||
#endif /* _ALTERA_TSE_H_ */
|
||||
|
|
|
|||
|
|
@ -33,6 +33,14 @@
|
|||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
|
||||
/*
|
||||
* MII/PHY
|
||||
*/
|
||||
#define CONFIG_CMD_MII 1
|
||||
#define CONFIG_PHY_GIGE 1
|
||||
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1
|
||||
#define CONFIG_PHY_MARVELL 1
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue