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https://github.com/brain-hackers/u-boot-brain
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9e75875849
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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|---|---|---|
| .. | ||
| cache.c | ||
| cmd_errata.c | ||
| commproc.c | ||
| config.mk | ||
| cpu_init_early.c | ||
| cpu_init_nand.c | ||
| cpu_init.c | ||
| cpu.c | ||
| ddr-gen1.c | ||
| ddr-gen2.c | ||
| ddr-gen3.c | ||
| ether_fcc.c | ||
| fdt.c | ||
| fixed_ivor.S | ||
| fsl_corenet2_serdes.c | ||
| fsl_corenet2_serdes.h | ||
| fsl_corenet_serdes.c | ||
| fsl_corenet_serdes.h | ||
| interrupts.c | ||
| liodn.c | ||
| Makefile | ||
| mp.c | ||
| mp.h | ||
| mpc8536_serdes.c | ||
| mpc8544_serdes.c | ||
| mpc8548_serdes.c | ||
| mpc8568_serdes.c | ||
| mpc8569_serdes.c | ||
| mpc8572_serdes.c | ||
| p1010_serdes.c | ||
| p1021_serdes.c | ||
| p1022_serdes.c | ||
| p1023_serdes.c | ||
| p2020_serdes.c | ||
| p2041_ids.c | ||
| p2041_serdes.c | ||
| p3041_ids.c | ||
| p3041_serdes.c | ||
| p4080_ids.c | ||
| p4080_serdes.c | ||
| p5020_ids.c | ||
| p5020_serdes.c | ||
| p5040_ids.c | ||
| p5040_serdes.c | ||
| pci.c | ||
| portals.c | ||
| qe_io.c | ||
| release.S | ||
| resetvec.S | ||
| serial_scc.c | ||
| speed.c | ||
| start.S | ||
| t4240_ids.c | ||
| t4240_serdes.c | ||
| tlb.c | ||
| traps.c | ||
| u-boot-nand_spl.lds | ||
| u-boot-nand.lds | ||
| u-boot.lds | ||