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https://github.com/brain-hackers/u-boot-brain
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Import octeon_should_swizzle_table[] which is needed for the area specific swapping. It will be used by the platform specific mangle-port.h header. Imported from Linux v5.7. Signed-off-by: Stefan Roese <sr@denx.de>
88 lines
2.1 KiB
C
88 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Marvell International Ltd.
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*/
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#include <asm/global_data.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/io.h>
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#include <mach/clock.h>
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#include <mach/cavm-reg.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* TRUE for devices having registers with little-endian byte
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* order, FALSE for registers with native-endian byte order.
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* PCI mandates little-endian, USB and SATA are configurable,
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* but we chose little-endian for these.
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*
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* This table will be referened in the Octeon platform specific
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* mangle-port.h header.
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*/
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const bool octeon_should_swizzle_table[256] = {
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[0x00] = true, /* bootbus/CF */
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[0x1b] = true, /* PCI mmio window */
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[0x1c] = true, /* PCI mmio window */
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[0x1d] = true, /* PCI mmio window */
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[0x1e] = true, /* PCI mmio window */
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[0x68] = true, /* OCTEON III USB */
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[0x69] = true, /* OCTEON III USB */
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[0x6c] = true, /* OCTEON III SATA */
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[0x6f] = true, /* OCTEON II USB */
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};
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static int get_clocks(void)
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{
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const u64 ref_clock = PLL_REF_CLK;
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void __iomem *rst_boot;
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u64 val;
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rst_boot = ioremap(CAVM_RST_BOOT, 0);
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val = ioread64(rst_boot);
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gd->cpu_clk = ref_clock * FIELD_GET(RST_BOOT_C_MUL, val);
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gd->bus_clk = ref_clock * FIELD_GET(RST_BOOT_PNR_MUL, val);
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debug("%s: cpu: %lu, bus: %lu\n", __func__, gd->cpu_clk, gd->bus_clk);
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return 0;
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}
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/* Early mach init code run from flash */
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int mach_cpu_init(void)
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{
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void __iomem *mio_boot_reg_cfg0;
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/* Remap boot-bus 0x1fc0.0000 -> 0x1f40.0000 */
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/* ToDo: Move this to an early running bus (bootbus) DM driver */
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mio_boot_reg_cfg0 = ioremap(CAVM_MIO_BOOT_REG_CFG0, 0);
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clrsetbits_be64(mio_boot_reg_cfg0, 0xffff, 0x1f40);
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/* Get clocks and store them in GD */
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get_clocks();
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return 0;
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}
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/**
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* Returns number of cores
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*
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* @return number of CPU cores for the specified node
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*/
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static int cavm_octeon_num_cores(void)
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{
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void __iomem *ciu_fuse;
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ciu_fuse = ioremap(CAVM_CIU_FUSE, 0);
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return fls64(ioread64(ciu_fuse) & 0xffffffffffff);
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}
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int print_cpuinfo(void)
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{
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printf("SoC: Octeon CN73xx (%d cores)\n", cavm_octeon_num_cores());
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return 0;
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}
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