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https://github.com/brain-hackers/u-boot-brain
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9db1bfa110
This is a port of the official PLL errata workaround from Freescale to mainline u-boot. The PLL's in the i.MX51 processor can go out of lock due to a metastable condition in an analog flip-flop when used at high frequencies. This workaround implements an undocumented feature in the PLL (dither mode), which causes the effect of this failure to be much lower (in terms of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. Signed-off-by: David Jander <david@protonic.nl> |
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| .. | ||
| mx5 | ||
| omap3 | ||
| omap4 | ||
| omap-common | ||
| s5p-common | ||
| s5pc1xx | ||
| s5pc2xx | ||
| tegra2 | ||
| u8500 | ||
| cache_v7.c | ||
| config.mk | ||
| cpu.c | ||
| Makefile | ||
| start.S | ||
| syslib.c | ||
| u-boot.lds | ||