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https://github.com/brain-hackers/u-boot-brain
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341e548eb8
In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015-2016 Marvell International Ltd.
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*/
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#ifndef _COMPHY_DATA_H_
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#define _COMPHY_DATA_H_
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#define COMPHY_SPEED_1_25G 0
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#define COMPHY_SPEED_2_5G 1
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#define COMPHY_SPEED_3_125G 2
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#define COMPHY_SPEED_5G 3
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#define COMPHY_SPEED_5_15625G 4
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#define COMPHY_SPEED_6G 5
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#define COMPHY_SPEED_10_3125G 6
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#define COMPHY_SPEED_MAX 7
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#define COMPHY_SPEED_INVALID 0xff
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#define COMPHY_TYPE_UNCONNECTED 0
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#define COMPHY_TYPE_PEX0 1
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#define COMPHY_TYPE_PEX1 2
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#define COMPHY_TYPE_PEX2 3
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#define COMPHY_TYPE_PEX3 4
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#define COMPHY_TYPE_SATA0 5
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#define COMPHY_TYPE_SATA1 6
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#define COMPHY_TYPE_SGMII0 7
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#define COMPHY_TYPE_SGMII1 8
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#define COMPHY_TYPE_SGMII2 9
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#define COMPHY_TYPE_USB3 10
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#define COMPHY_TYPE_USB3_HOST0 11
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#define COMPHY_TYPE_USB3_HOST1 12
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#define COMPHY_TYPE_USB3_DEVICE 13
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#define COMPHY_TYPE_RXAUI0 14
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#define COMPHY_TYPE_RXAUI1 15
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#define COMPHY_TYPE_SFI0 16
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#define COMPHY_TYPE_SFI1 17
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#define COMPHY_TYPE_AP 18
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#define COMPHY_TYPE_IGNORE 19
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#define COMPHY_TYPE_MAX 20
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#define COMPHY_TYPE_INVALID 0xff
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#define COMPHY_POLARITY_NO_INVERT 0
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#define COMPHY_POLARITY_TXD_INVERT 1
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#define COMPHY_POLARITY_RXD_INVERT 2
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#define COMPHY_POLARITY_ALL_INVERT \
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(COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT)
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#define UTMI_PHY_TO_USB3_HOST0 0
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#define UTMI_PHY_TO_USB3_HOST1 1
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#define UTMI_PHY_TO_USB3_DEVICE0 2
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#define UTMI_PHY_INVALID 0xff
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#endif /* _COMPHY_DATA_H_ */
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