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phy: marvell: add support for SFI1 

In CP115, comphy4 can be configured into SFI port1
(in addition to SFI0). This patch adds the option
described above.

In addition, rename all existing SFI/XFI references:
COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0

No functional change for exsiting configuration.

Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
This commit is contained in:
Igal Liberman 2018-05-14 11:20:54 +03:00 committed by Stefan Roese
parent a007f23626
commit 341e548eb8
10 changed files with 26 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/armada-7040-db.dts
View File

@ -132,7 +132,8 @@
};
phy2 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy3 {

4
arch/arm/dts/armada-8040-clearfog-gt-8k.dts
View File

@ -154,7 +154,7 @@
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: Not connected
* Lane 2: SFI (10G)
* Lane 2: SFI0 (10G)
* Lane 3: Not connected
* Lane 4: USB 3.0 host port1 (can be PCIe)
* Lane 5: Not connected
@ -166,7 +166,7 @@
phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy2 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
phy-type = <COMPHY_TYPE_UNCONNECTED>;

4
arch/arm/dts/armada-8040-db.dts
View File

@ -95,7 +95,7 @@
phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
phy-type = <COMPHY_TYPE_SATA1>;
@ -194,7 +194,7 @@
phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
phy-type = <COMPHY_TYPE_SATA1>;

4
arch/arm/dts/armada-8040-mcbin.dts
View File

@ -183,7 +183,7 @@
phy-type = <COMPHY_TYPE_PEX0>;
};
phy4 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SATA1>;
@ -299,7 +299,7 @@
phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SGMII2>;

4
arch/arm/dts/armada-8040-puzzle-m801.dts
View File

@ -234,7 +234,7 @@
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SATA1>;
@ -380,7 +380,7 @@
phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
phy-type = <COMPHY_TYPE_SGMII2>;

2
arch/arm/dts/cn9130-crb-A.dts
View File

@ -31,7 +31,7 @@
};
phy4 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};

2
arch/arm/dts/cn9130-crb-B.dts
View File

@ -31,7 +31,7 @@
};
phy4 {
phy-type = <COMPHY_TYPE_SFI>;
phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};

2
drivers/phy/marvell/comphy_core.c
View File

@ -41,7 +41,7 @@ static const char *get_type_string(u32 type)
"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
"SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
"USB3", "USB3_HOST0", "USB3_HOST1",
"USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP",
"USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP",
"IGNORE"
};

14
drivers/phy/marvell/comphy_cp110.c
View File

@ -109,10 +109,11 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
u32 lane)
{
int ret;
u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
debug_enter();
if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) {
if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
pr_err("Comphy %d isn't configured to SFI\n", lane);
return 0;
}
@ -630,13 +631,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
case COMPHY_TYPE_SFI:
mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
COMPHY_UNIT_ID0,
case COMPHY_TYPE_SFI0:
case COMPHY_TYPE_SFI1:
/* Calculate SFI id */
id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
ptr_chip_cfg->comphy_base_addr, lane, mode);
break;
case COMPHY_TYPE_RXAUI0:
case COMPHY_TYPE_RXAUI1:

9
include/dt-bindings/comphy/comphy_data.h
View File

@ -32,10 +32,11 @@
#define COMPHY_TYPE_USB3_DEVICE 13
#define COMPHY_TYPE_RXAUI0 14
#define COMPHY_TYPE_RXAUI1 15
#define COMPHY_TYPE_SFI 16
#define COMPHY_TYPE_AP 17
#define COMPHY_TYPE_IGNORE 18
#define COMPHY_TYPE_MAX 19
#define COMPHY_TYPE_SFI0 16
#define COMPHY_TYPE_SFI1 17
#define COMPHY_TYPE_AP 18
#define COMPHY_TYPE_IGNORE 19
#define COMPHY_TYPE_MAX 20
#define COMPHY_TYPE_INVALID 0xff
#define COMPHY_POLARITY_NO_INVERT 0