From 341e548eb8f586c39c49efbd0b90eaf283fbee63 Mon Sep 17 00:00:00 2001 From: Igal Liberman Date: Mon, 14 May 2018 11:20:54 +0300 Subject: [PATCH] phy: marvell: add support for SFI1 In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman Signed-off-by: Konstantin Porotchkin --- arch/arm/dts/armada-7040-db.dts | 3 ++- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 4 ++-- arch/arm/dts/armada-8040-db.dts | 4 ++-- arch/arm/dts/armada-8040-mcbin.dts | 4 ++-- arch/arm/dts/armada-8040-puzzle-m801.dts | 4 ++-- arch/arm/dts/cn9130-crb-A.dts | 2 +- arch/arm/dts/cn9130-crb-B.dts | 2 +- drivers/phy/marvell/comphy_core.c | 2 +- drivers/phy/marvell/comphy_cp110.c | 14 ++++++++------ include/dt-bindings/comphy/comphy_data.h | 9 +++++---- 10 files changed, 26 insertions(+), 22 deletions(-) diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index f475fb3610..b158f92349 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -132,7 +132,8 @@ }; phy2 { - phy-type = ; + phy-type = ; + phy-speed = ; }; phy3 { diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index ce5832c2fb..6a586dbbba 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -154,7 +154,7 @@ * CP0 Serdes Configuration: * Lane 0: PCIe0 (x1) * Lane 1: Not connected - * Lane 2: SFI (10G) + * Lane 2: SFI0 (10G) * Lane 3: Not connected * Lane 4: USB 3.0 host port1 (can be PCIe) * Lane 5: Not connected @@ -166,7 +166,7 @@ phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { phy-type = ; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 1edfaab682..51c2f23f4d 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -95,7 +95,7 @@ phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { phy-type = ; @@ -194,7 +194,7 @@ phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { phy-type = ; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index a6ef40138d..2184648318 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -183,7 +183,7 @@ phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; @@ -299,7 +299,7 @@ phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index 0becc4ff0d..510fb84d5a 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -234,7 +234,7 @@ phy-speed = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; @@ -380,7 +380,7 @@ phy-speed = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts index 5c5e0fb2eb..fcfcd15d8d 100644 --- a/arch/arm/dts/cn9130-crb-A.dts +++ b/arch/arm/dts/cn9130-crb-A.dts @@ -31,7 +31,7 @@ }; phy4 { - phy-type = ; + phy-type = ; phy-speed = ; }; diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts index 6041084a2c..b681b6032d 100644 --- a/arch/arm/dts/cn9130-crb-B.dts +++ b/arch/arm/dts/cn9130-crb-B.dts @@ -31,7 +31,7 @@ }; phy4 { - phy-type = ; + phy-type = ; phy-speed = ; }; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 9293607926..2c9d7b2288 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -41,7 +41,7 @@ static const char *get_type_string(u32 type) "UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3", "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2", "USB3", "USB3_HOST0", "USB3_HOST1", - "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP", + "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP", "IGNORE" }; diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 349109b6dc..576538feb7 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -109,10 +109,11 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, u32 lane) { int ret; + u32 type = ptr_chip_cfg->comphy_map_data[lane].type; debug_enter(); - if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) { + if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) { pr_err("Comphy %d isn't configured to SFI\n", lane); return 0; } @@ -630,13 +631,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case COMPHY_TYPE_SFI: - mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, - COMPHY_UNIT_ID0, + case COMPHY_TYPE_SFI0: + case COMPHY_TYPE_SFI1: + /* Calculate SFI id */ + id = ptr_comphy_map->type - COMPHY_TYPE_SFI0; + mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id, ptr_comphy_map->speed); ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, - ptr_chip_cfg->comphy_base_addr, lane, - mode); + ptr_chip_cfg->comphy_base_addr, lane, mode); break; case COMPHY_TYPE_RXAUI0: case COMPHY_TYPE_RXAUI1: diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 8e92705989..8353a78740 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -32,10 +32,11 @@ #define COMPHY_TYPE_USB3_DEVICE 13 #define COMPHY_TYPE_RXAUI0 14 #define COMPHY_TYPE_RXAUI1 15 -#define COMPHY_TYPE_SFI 16 -#define COMPHY_TYPE_AP 17 -#define COMPHY_TYPE_IGNORE 18 -#define COMPHY_TYPE_MAX 19 +#define COMPHY_TYPE_SFI0 16 +#define COMPHY_TYPE_SFI1 17 +#define COMPHY_TYPE_AP 18 +#define COMPHY_TYPE_IGNORE 19 +#define COMPHY_TYPE_MAX 20 #define COMPHY_TYPE_INVALID 0xff #define COMPHY_POLARITY_NO_INVERT 0