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https://github.com/brain-hackers/u-boot-brain
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![Vabhav Sharma](/assets/img/avatar_default.png)
LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
115 lines
2.7 KiB
C
115 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <netdev.h>
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#include <fm_eth.h>
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#include <fsl_dtsec.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include "../common/fman.h"
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct memac_mdio_info dtsec_mdio_info;
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struct mii_dev *dev;
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u32 srds_s1;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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dtsec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fm_memac_mdio_init(bis, &dtsec_mdio_info);
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/* QSGMII on lane B, MAC 6/5/10/1 */
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fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
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switch (srds_s1) {
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case 0x3040:
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break;
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default:
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printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
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srds_s1);
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break;
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}
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dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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fm_info_set_mdio(FM1_DTSEC6, dev);
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fm_info_set_mdio(FM1_DTSEC5, dev);
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fm_info_set_mdio(FM1_DTSEC10, dev);
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fm_info_set_mdio(FM1_DTSEC1, dev);
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cpu_eth_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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#ifdef CONFIG_FMAN_ENET
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int fdt_update_ethernet_dt(void *blob)
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{
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u32 srds_s1;
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int i, prop;
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int offset, nodeoff;
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const char *path;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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/* Cycle through all aliases */
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for (prop = 0; ; prop++) {
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const char *name;
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/* FDT might have been edited, recompute the offset */
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offset = fdt_first_property_offset(blob,
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fdt_path_offset(blob,
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"/aliases")
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);
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/* Select property number 'prop' */
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for (i = 0; i < prop; i++)
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offset = fdt_next_property_offset(blob, offset);
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if (offset < 0)
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break;
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path = fdt_getprop_by_offset(blob, offset, &name, NULL);
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nodeoff = fdt_path_offset(blob, path);
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switch (srds_s1) {
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case 0x3040:
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if (!strcmp(name, "ethernet1"))
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fdt_status_disabled(blob, nodeoff);
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if (!strcmp(name, "ethernet2"))
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fdt_status_disabled(blob, nodeoff);
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if (!strcmp(name, "ethernet3"))
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fdt_status_disabled(blob, nodeoff);
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if (!strcmp(name, "ethernet6"))
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fdt_status_disabled(blob, nodeoff);
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break;
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default:
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printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n",
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__func__, srds_s1);
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break;
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}
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}
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return 0;
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}
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#endif
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