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https://github.com/brain-hackers/u-boot-brain
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![Arkadiusz Karas](/assets/img/avatar_default.png)
Add iMX6ULL VisionSOM SoM and VisionCB-RT-STD evaluation board support. The SoM has an iMX6ULL, 512 MiB of DRAM and microSD slot. The carrier board has Ethernet, USB host port, USB OTG port. Signed-off-by: Arkadiusz Karas <arkadiusz.karas@somlabs.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
277 lines
5.4 KiB
Plaintext
277 lines
5.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017-2019 SoMLabs
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "imx6ull.dtsi"
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/ {
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model = "SoMLabs VisionSOM-6ULL";
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compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
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chosen {
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stdout-path = &uart1;
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};
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memory {
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reg = <0x80000000 0x20000000>;
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};
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leds {
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compatible = "gpio-leds";
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usr0 {
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label = "usr0";
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gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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usr1 {
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label = "usr1";
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gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc0";
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};
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usr2 {
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label = "usr2";
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gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc1";
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};
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usr3 {
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label = "usr3";
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gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usb_otg1_vbus: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg2_vbus: regulator@3 {
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compatible = "regulator-fixed";
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reg = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg2>;
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regulator-name = "usb_otg2_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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};
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&cpu0 {
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arm-supply = <®_arm>;
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soc-supply = <®_soc>;
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&gpc {
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fsl,cpu_pupscr_sw2iso = <0x1>;
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fsl,cpu_pupscr_sw = <0x0>;
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fsl,cpu_pdnscr_iso2sw = <0x1>;
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fsl,cpu_pdnscr_iso = <0x1>;
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fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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};
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&i2c2 {
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clock_frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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/* 32kHz low power reference clock for WiFi */
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MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099
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/* LED 0..3 */
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MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099
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MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099
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MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099
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MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
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MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
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>;
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};
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pinctrl_tsc: tscgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
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MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
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MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
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MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0
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>;
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};
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pinctrl_usb_otg1: usbotg1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
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MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0
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>;
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};
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pinctrl_usb_otg2: usbotg2grp {
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fsl,pins = <
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MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0
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>;
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};
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};
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&tsc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc>;
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xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
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measure-delay-time = <0xffff>;
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pre-charge-time = <0xfff>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1>;
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dr_mode = "otg";
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbotg2 {
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vbus-supply = <®_usb_otg2_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&usbphy1 {
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tx-d-cal = <0x5>;
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};
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&usbphy2 {
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tx-d-cal = <0x5>;
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};
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&usdhc2 {
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non-removable;
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disable-wp;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,wdog_b;
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};
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