ARM: imx: mx6ull: Add iMX6ULL VisionSOM SoM and EVK
Add iMX6ULL VisionSOM SoM and VisionCB-RT-STD evaluation board support. The SoM has an iMX6ULL, 512 MiB of DRAM and microSD slot. The carrier board has Ethernet, USB host port, USB OTG port. Signed-off-by: Arkadiusz Karas <arkadiusz.karas@somlabs.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Arkadiusz Karas
Stefano Babic
parent
9d12303322
commit
5b6f8f3083
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@ -676,6 +676,7 @@ dtb-$(CONFIG_MX6ULL) += \
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imx6ull-colibri.dtb \
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imx6ull-phytec-segin-ff-rdk-emmc.dtb \
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imx6ull-dart-6ul.dtb \
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imx6ull-somlabs-visionsom.dtb \
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imx6ulz-14x14-evk.dtb
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dtb-$(CONFIG_ARCH_MX6) += \
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@ -0,0 +1,276 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017-2019 SoMLabs
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include "imx6ull.dtsi"
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/ {
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model = "SoMLabs VisionSOM-6ULL";
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compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull";
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chosen {
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stdout-path = &uart1;
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};
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memory {
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reg = <0x80000000 0x20000000>;
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};
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leds {
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compatible = "gpio-leds";
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usr0 {
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label = "usr0";
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gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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usr1 {
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label = "usr1";
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gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc0";
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};
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usr2 {
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label = "usr2";
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gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "mmc1";
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};
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usr3 {
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label = "usr3";
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gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usb_otg1_vbus: regulator@2 {
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compatible = "regulator-fixed";
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reg = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1>;
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regulator-name = "usb_otg1_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usb_otg2_vbus: regulator@3 {
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compatible = "regulator-fixed";
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reg = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg2>;
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regulator-name = "usb_otg2_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio2 8 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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};
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&cpu0 {
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arm-supply = <®_arm>;
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soc-supply = <®_soc>;
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&gpc {
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fsl,cpu_pupscr_sw2iso = <0x1>;
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fsl,cpu_pupscr_sw = <0x0>;
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fsl,cpu_pdnscr_iso2sw = <0x1>;
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fsl,cpu_pdnscr_iso = <0x1>;
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fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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};
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&i2c2 {
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clock_frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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/* 32kHz low power reference clock for WiFi */
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MX6UL_PAD_JTAG_TCK__OSC32K_32K_OUT 0x17099
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/* LED 0..3 */
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MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x17099
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MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x17099
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MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x17099
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MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x17099
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1F829
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400010a9
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
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MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
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MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
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>;
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};
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pinctrl_tsc: tscgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
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MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
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MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
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MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
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MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
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MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
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MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
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MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
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MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
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MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x30b0
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>;
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};
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pinctrl_usb_otg1: usbotg1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
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MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x10b0
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>;
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};
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pinctrl_usb_otg2: usbotg2grp {
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fsl,pins = <
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MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x10b0
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>;
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};
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};
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&tsc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_tsc>;
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xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
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measure-delay-time = <0xffff>;
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pre-charge-time = <0xfff>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1>;
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dr_mode = "otg";
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&usbotg2 {
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vbus-supply = <®_usb_otg2_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&usbphy1 {
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tx-d-cal = <0x5>;
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};
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&usbphy2 {
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tx-d-cal = <0x5>;
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};
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&usdhc2 {
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non-removable;
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disable-wp;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,wdog_b;
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};
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@ -540,6 +540,18 @@ config TARGET_SKSIMX6
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bool "sks-imx6"
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select SUPPORT_SPL
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config TARGET_SOMLABS_VISIONSOM_6ULL
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bool "visionsom-6ull"
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select MX6ULL
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select BOARD_LATE_INIT
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select DM
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select DM_ETH
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select DM_GPIO
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select DM_MMC
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select DM_SERIAL
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select DM_THERMAL
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imply CMD_DM
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config TARGET_TBS2910
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bool "TBS2910 Matrix ARM mini PC"
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@ -694,6 +706,7 @@ source "board/logicpd/imx6/Kconfig"
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source "board/seco/Kconfig"
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source "board/sks-kinkel/sksimx6/Kconfig"
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source "board/solidrun/mx6cuboxi/Kconfig"
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source "board/somlabs/visionsom-6ull/Kconfig"
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source "board/technexion/pico-imx6/Kconfig"
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source "board/technexion/pico-imx6ul/Kconfig"
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source "board/tbs/tbs2910/Kconfig"
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@ -0,0 +1,12 @@
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if TARGET_SOMLABS_VISIONSOM_6ULL
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config SYS_BOARD
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default "visionsom-6ull"
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config SYS_VENDOR
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default "somlabs"
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config SYS_CONFIG_NAME
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default "somlabs_visionsom_6ull"
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endif
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@ -0,0 +1,6 @@
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VISIONSOM-6ULL BOARD
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M: Arkadiusz Karas <arkadiusz.karas@somlabs.com>
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S: Maintained
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F: board/somlabs/visionsom-6ull/
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F: include/configs/somlabs_visionsom_6ull.h
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F: configs/somlabs_visionsom_6ull_defconfig
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0+
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# (C) Copyright 2019 Arkadiusz Karas <arkadiusz.karas@somlabs.com>
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obj-y := visionsom-6ull.o
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@ -0,0 +1,107 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 A. Karas
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : sd
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*/
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BOOT_FROM sd
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/*
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* Secure boot support
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*/
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#ifdef CONFIG_IMX_HAB
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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/* Micron MT41K256M16TW-107 */
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/* Enable all clocks */
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DATA 4 0x020c4068 0xffffffff
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DATA 4 0x020c406c 0xffffffff
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DATA 4 0x020c4070 0xffffffff
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DATA 4 0x020c4074 0xffffffff
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DATA 4 0x020c4078 0xffffffff
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DATA 4 0x020c407c 0xffffffff
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DATA 4 0x020c4080 0xffffffff
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DATA 4 0x020E04B4 0x000C0000
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DATA 4 0x020E04AC 0x00000000
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DATA 4 0x020E027C 0x00000030
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DATA 4 0x020E0250 0x00000030
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DATA 4 0x020E024C 0x00000030
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DATA 4 0x020E0490 0x00000030
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DATA 4 0x020E0288 0x00000030
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DATA 4 0x020E0270 0x00000000
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DATA 4 0x020E0260 0x00000030
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DATA 4 0x020E0264 0x00000030
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DATA 4 0x020E04A0 0x00000030
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DATA 4 0x020E0494 0x00020000
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DATA 4 0x020E0280 0x00000030
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DATA 4 0x020E0284 0x00000030
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DATA 4 0x020E04B0 0x00020000
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DATA 4 0x020E0498 0x00000030
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DATA 4 0x020E04A4 0x00000030
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DATA 4 0x020E0244 0x00000030
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DATA 4 0x020E0248 0x00000030
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B0800 0xA1390003
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DATA 4 0x021B080C 0x00000000
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DATA 4 0x021B083C 0x41570155
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DATA 4 0x021B0848 0x4040474A
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DATA 4 0x021B0850 0x40405550
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DATA 4 0x021B081C 0x33333333
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DATA 4 0x021B0820 0x33333333
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DATA 4 0x021B082C 0xf3333333
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DATA 4 0x021B0830 0xf3333333
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DATA 4 0x021B08C0 0x00921012
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DATA 4 0x021B08b8 0x00000800
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DATA 4 0x021B0004 0x0002002D
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DATA 4 0x021B0008 0x1B333030
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DATA 4 0x021B000C 0x676B52F3
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DATA 4 0x021B0010 0xB66D0B63
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DATA 4 0x021B0014 0x01FF00DB
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DATA 4 0x021B0018 0x00201740
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DATA 4 0x021B001C 0x00008000
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DATA 4 0x021B002C 0x000026D2
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DATA 4 0x021B0030 0x006B1023
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DATA 4 0x021B0040 0x0000004F
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DATA 4 0x021B0000 0x84180000
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DATA 4 0x021B0890 0x23400A38
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DATA 4 0x021B001C 0x02008032
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DATA 4 0x021B001C 0x00008033
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DATA 4 0x021B001C 0x00048031
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DATA 4 0x021B001C 0x15208030
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DATA 4 0x021B001C 0x04008040
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DATA 4 0x021B0020 0x00000800
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DATA 4 0x021B0818 0x00000227
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DATA 4 0x021B0004 0x0002552D
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DATA 4 0x021B0404 0x00011006
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DATA 4 0x021B001C 0x00000000
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@ -0,0 +1,146 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017-2019 A. Karas, SomLabs
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <init.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <common.h>
|
||||
#include <env.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <linux/sizes.h>
|
||||
#include <mmc.h>
|
||||
#include <netdev.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = imx_ddr_size();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
static int setup_fec(void)
|
||||
{
|
||||
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Use 50M anatop loopback REF_CLK1 for ENET1,
|
||||
* clear gpr1[13], set gpr1[17].
|
||||
*/
|
||||
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
|
||||
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
|
||||
|
||||
ret = enable_fec_anatop_clock(0, ENET_50MHZ);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
enable_enet_clk(1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int mmc_map_to_kernel_blk(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FEC_MXC
|
||||
setup_fec();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* 4 bit bus width */
|
||||
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
|
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
|
||||
{NULL, 0},
|
||||
};
|
||||
#endif
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
if (is_cpu_type(MXC_CPU_MX6ULL))
|
||||
env_set("board", "visionsom-6ull");
|
||||
else
|
||||
env_set("board", "visionsom-6ul");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Board: SoMLabs VisionSOM-6UL%s\n",
|
||||
is_cpu_type(MXC_CPU_MX6ULL) ? "L" : "");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SYS_TEXT_BASE=0x87800000
|
||||
CONFIG_TARGET_SOMLABS_VISIONSOM_6ULL=y
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xC0000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/somlabs/visionsom-6ull/imximage.cfg"
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_BOUNCE_BUFFER=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_MEMTEST=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
# CONFIG_CMD_MDIO is not set
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-somlabs-visionsom"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ8XXX=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX6=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_LZO=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
@ -0,0 +1,116 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2017-2019 A. Karas, SomLabs
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the SoMlabs VisionSOM 6ULL board.
|
||||
*/
|
||||
#ifndef __SOMLABS_VISIONSOM_6ULL_H
|
||||
#define __SOMLABS_VISIONSOM_6ULL_H
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <linux/sizes.h>
|
||||
#include "mx6_common.h"
|
||||
#include <asm/mach-imx/gpio.h>
|
||||
|
||||
/* SPL options */
|
||||
#include "imx6_spl.h"
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
|
||||
|
||||
#define CONFIG_MXC_UART
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* MMC Configs */
|
||||
#ifdef CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
#endif /* CONFIG_FSL_USDHC */
|
||||
|
||||
#define CONFIG_CMD_READ
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootm_size=0x10000000\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"initrd_addr=0x86800000\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"splashimage=0x80000000\0" \
|
||||
"splashfile=/boot/splash.bmp\0" \
|
||||
"mmcdev=1\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk1p1 rootwait rw\0" \
|
||||
"setrootmmc=setenv rootspec root=${mmcroot}\0" \
|
||||
"setbootscriptmmc=setenv loadbootscript " \
|
||||
"load mmc ${mmcdev}:${mmcpart} " \
|
||||
"${loadaddr} /boot/${script};\0" \
|
||||
"setloadmmc=setenv loadimage load mmc ${mmcdev}:${mmcpart} " \
|
||||
"${loadaddr} /boot/${image}; " \
|
||||
"setenv loadfdt load mmc ${mmcdev}:${mmcpart} " \
|
||||
"${fdt_addr} /boot/${fdt_file};\0" \
|
||||
"setbootargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"${rootspec}\0" \
|
||||
"execbootscript=echo Running bootscript...; source\0" \
|
||||
"setfdtfile=setenv fdt_file somlabs-visionsom-6ull.dtb\0" \
|
||||
"checkbootdev=run setbootscriptmmc; " \
|
||||
"run setrootmmc; " \
|
||||
"run setloadmmc; " \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"run setfdtfile; " \
|
||||
"run checkbootdev; " \
|
||||
"run loadfdt;" \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run setbootargs; " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"fi; " \
|
||||
"fi"
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* environment organization */
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
|
||||
/* USB Configs */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_MXC_PHYADDR 0x1
|
||||
#define CONFIG_FEC_XCV_TYPE RMII
|
||||
#define CONFIG_ETHPRIME "eth0"
|
||||
#endif
|
||||
|
||||
#define CONFIG_IMX_THERMAL
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue