Valentin Longchamp 7e157b0ade mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it ... If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 RAM chips (no module used, chips directly soldered on board with an SPD EEPROM). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h, lc_common_dimm_params.c, common_timing_params.h] Acked-by: York Sun <yorksun@freescale.com>		2013-10-24 09:35:52 -07:00
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ddr	mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it	2013-10-24 09:35:52 -07:00
cpu.c	powerpc/85xx: Add C29x SoC support	2013-08-09 12:41:42 -07:00
fdt.c	powerpc/usb:Define CONFIG_USB_MAX_CONTROLLER_COUNT for all 85xx socs	2013-10-24 09:35:03 -07:00
fsl_ifc.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
fsl_lbc.c	arch/powerpc/cpu/mpc8xxx/: sparse fixes	2012-11-04 11:00:36 -07:00
law.c	powerpc: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and enabled some functionality for common SPL	2013-08-20 09:47:15 -07:00
Makefile	spl/powerpc: introduce CONFIG_SPL_INIT_MINIMAL	2012-11-26 15:41:24 -06:00
srio.c	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00