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powerpc/85xx: Add C29x SoC support
The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
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@ -46,6 +46,7 @@ COBJS-$(CONFIG_MPC8568) += ddr-gen2.o
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COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
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# supports ddr1/2/3
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COBJS-$(CONFIG_PPC_C29X) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8572) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8536) += ddr-gen3.o
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COBJS-$(CONFIG_MPC8569) += ddr-gen3.o
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@ -100,6 +101,7 @@ COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o
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COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
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# SoC specific SERDES support
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COBJS-$(CONFIG_PPC_C29X) += c29x_serdes.o
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COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o
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COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o
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COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
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65
arch/powerpc/cpu/mpc85xx/c29x_serdes.c
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65
arch/powerpc/cpu/mpc85xx/c29x_serdes.c
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@ -0,0 +1,65 @@
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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static u32 serdes1_prtcl_map;
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struct serdes_config {
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u32 protocol;
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u8 lanes[SRDS1_MAX_LANES];
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};
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static const struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{1, {PCIE1, PCIE1, PCIE1, PCIE1} },
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{2, {PCIE1, PCIE1, PCIE1, PCIE1} },
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{3, {PCIE1, PCIE1, NONE, NONE} },
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{4, {PCIE1, PCIE1, NONE, NONE} },
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{5, {PCIE1, NONE, NONE, NONE} },
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{6, {PCIE1, NONE, NONE, NONE} },
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{}
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};
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int is_serdes_configured(enum srds_prtcl device)
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{
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return (1 << device) & serdes1_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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const struct serdes_config *ptr;
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int lane;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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ptr = &serdes1_cfg_tbl[srds_cfg];
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if (!ptr->protocol)
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return;
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = ptr->lanes[lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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}
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@ -79,6 +79,9 @@ static struct cpu_type cpu_type_list[] = {
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CPU_TYPE_ENTRY(BSC9131, 9131, 1),
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CPU_TYPE_ENTRY(BSC9132, 9132, 2),
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CPU_TYPE_ENTRY(BSC9232, 9232, 2),
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CPU_TYPE_ENTRY(C291, C291, 1),
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CPU_TYPE_ENTRY(C292, C292, 1),
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CPU_TYPE_ENTRY(C293, C293, 1),
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#elif defined(CONFIG_MPC86xx)
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CPU_TYPE_ENTRY(8610, 8610, 1),
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CPU_TYPE_ENTRY(8641, 8641, 2),
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@ -626,6 +626,18 @@
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#elif defined(CONFIG_PPC_C29X)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_TSECV2_1
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#define CONFIG_SYS_FSL_SEC_COMPAT 6
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#else
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#error Processor type not defined for this platform
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#endif
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@ -92,6 +92,7 @@ enum law_trgt_if {
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LAW_TRGT_IF_LBC = 0x04,
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LAW_TRGT_IF_CCSR = 0x08,
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LAW_TRGT_IF_DSP_CCSR = 0x09,
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LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
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LAW_TRGT_IF_DDR_INTRLV = 0x0b,
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LAW_TRGT_IF_RIO = 0x0c,
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#if defined(CONFIG_BSC9132)
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@ -2147,6 +2147,11 @@ typedef struct ccsr_gur {
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#ifdef CONFIG_MPC8536
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#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
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#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
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#elif defined(CONFIG_PPC_C29X)
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#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
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#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
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& MPC85xx_PORDEVSR2_DDR_SPD_0) \
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>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
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#else
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#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
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#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
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@ -2194,6 +2199,9 @@ typedef struct ccsr_gur {
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#elif defined(CONFIG_BSC9132)
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#define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
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#elif defined(CONFIG_PPC_C29X)
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#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
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#else
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#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
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@ -2209,6 +2217,10 @@ typedef struct ccsr_gur {
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#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
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u32 pordbgmsr; /* POR debug mode status */
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u32 pordevsr2; /* POR I/O device status 2 */
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#if defined(CONFIG_PPC_C29X)
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#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
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#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
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#endif
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/* The 8544 RM says this is bit 26, but it's really bit 24 */
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#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
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u8 res1[8];
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@ -2354,6 +2366,11 @@ typedef struct ccsr_gur {
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#ifdef CONFIG_BSC9132
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#define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
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#define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
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#endif
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#if defined(CONFIG_PPC_C29X)
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#define MPC85xx_PMUXCR_SPI_MASK 0x00000300
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#define MPC85xx_PMUXCR_SPI 0x00000000
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#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
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#endif
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u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
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#if defined(CONFIG_P1010) || defined(CONFIG_P1014)
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@ -3026,12 +3043,18 @@ struct ccsr_pman {
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#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
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#ifdef CONFIG_TSECV2
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#define CONFIG_SYS_TSEC1_OFFSET 0xB0000
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#elif defined(CONFIG_TSECV2_1)
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#define CONFIG_SYS_TSEC1_OFFSET 0x10000
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#else
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#endif
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#define CONFIG_SYS_MDIO1_OFFSET 0x24000
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#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
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#if defined(CONFIG_PPC_C29X)
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#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
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#else
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#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
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#endif
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#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
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#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
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#define CONFIG_SYS_SNVS_OFFSET 0xE6000
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@ -1119,6 +1119,9 @@
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#define SVR_T4240 0x824000
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#define SVR_T4120 0x824001
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#define SVR_T4160 0x824100
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#define SVR_C291 0x850000
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#define SVR_C292 0x850020
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#define SVR_C293 0x850030
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#define SVR_B4860 0X868000
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#define SVR_G4860 0x868001
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#define SVR_G4060 0x868003
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