mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
8f74e659c4
Due to how the Makefile logic is we currently get DM_SPI support in SPL enabled by having DM_SPI enabled for full U-Boot but not having CONFIG_SPL_DM_SPI set. Add this missing option to boards that were inadvertently making use of it. Cc: Adam Ford <aford173@gmail.com> Cc: Akash Gajjar <akash@openedev.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Andy Yan <andy.yan@rock-chips.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Chee Hong Ang <chee.hong.ang@intel.com> Cc: Chin-Liang See <clsee@altera.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Klaus Goger <klaus.goger@theobroma-systems.com> Cc: Levin Du <djw@t-chip.com.cn> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Luca Ceresoli <luca@lucaceresoli.net> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <monstr@monstr.eu> Cc: Mike Looijmans <mike.looijmans@topic.nl> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Pavel Machek <pavel@denx.de> Cc: Peter Robinson <pbrobinson@gmail.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Suniel Mahesh <sunil@amarulasolutions.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Wolfgang Grandegger <wg@aries-embedded.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
69 lines
1.8 KiB
Plaintext
69 lines
1.8 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_ENV_SIZE=0x4000
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CONFIG_ENV_OFFSET=0xE0000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
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CONFIG_DM_GPIO=y
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CONFIG_SPL_DM_SPI=y
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CONFIG_SYS_BOOTCOUNT_ADDR=0xfffffff8
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CONFIG_TARGET_SOCFPGA_SR1500=y
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CONFIG_ENV_OFFSET_REDUND=0xF0000
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CONFIG_SPL_TEXT_BASE=0xFFFF0000
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CONFIG_DISTRO_DEFAULTS=y
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CONFIG_FIT=y
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# CONFIG_USE_BOOTCOMMAND is not set
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
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CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_sr1500.dtb"
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CONFIG_VERSION_VARIABLE=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_CMD_ASKENV=y
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CONFIG_CMD_GREPENV=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_SYS_MEMTEST_START=0x00000000
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CONFIG_SYS_MEMTEST_END=0x40000000
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
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CONFIG_CMD_UBI=y
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# CONFIG_ISO_PARTITION is not set
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# CONFIG_EFI_PARTITION is not set
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_BOOTCOUNT_LIMIT=y
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CONFIG_DWAPB_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_DW=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_DW=y
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CONFIG_MTD=y
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CONFIG_SF_DEFAULT_SPEED=100000000
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CONFIG_SPI_FLASH_STMICRO=y
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# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
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CONFIG_SPI_FLASH_MTD=y
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CONFIG_PHY_MARVELL=y
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CONFIG_DM_ETH=y
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CONFIG_PHY_GIGE=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_MII=y
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CONFIG_DM_RESET=y
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CONFIG_SPI=y
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CONFIG_CADENCE_QSPI=y
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# CONFIG_SPL_WDT is not set
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