Marek Vasut 8e9e62c946 ddr: altera: Fix scc_mgr_set() argument order ... The code should be setting registers to zero, not one register to value. Swap the order of arguments to correct the behavior. The behavior is now in-line with code generated by Quartus 15.1 . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>		2016-04-20 11:28:44 +02:00
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Makefile	driver/ddr/altera: Add the sdram calibration portion	2015-08-08 14:14:05 +02:00
sdram.c	ddr: altera: Init the rule ID in debug code	2016-01-16 07:07:22 +01:00
sequencer.c	ddr: altera: Fix scc_mgr_set() argument order	2016-04-20 11:28:44 +02:00
sequencer.h	ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL	2015-08-08 14:14:29 +02:00