mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
8cb4817d0f
Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
103 lines
2.4 KiB
C
103 lines
2.4 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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DECLARE_GLOBAL_DATA_PTR;
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void mips_cache_probe(void)
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{
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#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
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unsigned long conf1, il, dl;
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conf1 = read_c0_config1();
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il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
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dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
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gd->arch.l1i_line_size = il ? (2 << il) : 0;
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gd->arch.l1d_line_size = dl ? (2 << dl) : 0;
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#endif
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}
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static inline unsigned long icache_line_size(void)
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{
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#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
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return gd->arch.l1i_line_size;
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#else
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return CONFIG_SYS_ICACHE_LINE_SIZE;
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#endif
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}
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static inline unsigned long dcache_line_size(void)
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{
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#ifdef CONFIG_SYS_CACHE_SIZE_AUTO
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return gd->arch.l1d_line_size;
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#else
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return CONFIG_SYS_DCACHE_LINE_SIZE;
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#endif
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}
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#define cache_loop(start, end, lsize, ops...) do { \
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const void *addr = (const void *)(start & ~(lsize - 1)); \
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const void *aend = (const void *)((end - 1) & ~(lsize - 1)); \
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const unsigned int cache_ops[] = { ops }; \
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unsigned int i; \
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\
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for (; addr <= aend; addr += lsize) { \
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for (i = 0; i < ARRAY_SIZE(cache_ops); i++) \
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mips_cache(cache_ops[i], addr); \
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} \
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} while (0)
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void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long ilsize = icache_line_size();
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unsigned long dlsize = dcache_line_size();
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/* aend will be miscalculated when size is zero, so we return here */
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if (size == 0)
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return;
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if (ilsize == dlsize) {
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/* flush I-cache & D-cache simultaneously */
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cache_loop(start_addr, start_addr + size, ilsize,
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HIT_WRITEBACK_INV_D, HIT_INVALIDATE_I);
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return;
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}
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/* flush D-cache */
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cache_loop(start_addr, start_addr + size, dlsize, HIT_WRITEBACK_INV_D);
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/* flush I-cache */
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cache_loop(start_addr, start_addr + size, ilsize, HIT_INVALIDATE_I);
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}
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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/* aend will be miscalculated when size is zero, so we return here */
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if (start_addr == stop)
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return;
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cache_loop(start_addr, stop, lsize, HIT_WRITEBACK_INV_D);
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}
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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/* aend will be miscalculated when size is zero, so we return here */
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if (start_addr == stop)
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return;
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cache_loop(start_addr, stop, lsize, HIT_INVALIDATE_D);
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}
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