Bin Meng a6d7e8c914 riscv: Split SiFive CLINT support between SPL and U-Boot proper ... At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>		2021-05-17 16:42:24 +08:00
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ax25	cpu: Rename SPL_CPU_SUPPORT to SPL_CPU	2021-03-27 15:04:31 +13:00
fu540	riscv: Split SiFive CLINT support between SPL and U-Boot proper	2021-05-17 16:42:24 +08:00
generic	riscv: Split SiFive CLINT support between SPL and U-Boot proper	2021-05-17 16:42:24 +08:00
cpu.c	riscv: cpu: Add callback to init each core	2021-05-05 16:11:22 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: cpu: Add callback to init each core	2021-05-05 16:11:22 +08:00
u-boot-spl.lds	riscv: Add _image_binary_end for SPL	2020-06-04 09:44:08 +08:00
u-boot.lds	riscv: Fix breakage caused by linker relaxation	2020-02-10 14:50:53 +08:00