Suman Anna 7873e9df8f armv8: K3: j7200: Add custom MMU support ... The A72 U-Boot code can load and boot a number of the available R5FSS Cores on the J7200 SoC. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. The J7200 SoC has less number of remote processors compared to J721E, so use less memory for the remote processors. So, a separate table based on the current J721E table is added for J7200 SoCs, and selected using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol. Signed-off-by: Suman Anna <s-anna@ti.com>		2020-09-15 18:51:53 +05:30
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include/mach	arm: mach-k3: Add HyperFlash boot mode support	2020-09-15 18:51:52 +05:30
am6_init.c	arm: mach-k3: sysfw-loader: Add support for rom loading sysfw image	2020-08-11 20:34:46 +05:30
arm64-mmu.c	armv8: K3: j7200: Add custom MMU support	2020-09-15 18:51:53 +05:30
cache.S	arm: mach-k3: Clean non-coherent lines out of L3 cache	2020-08-11 10:18:27 +05:30
common.c	arm: mach-k3: j7200: Detect if ROM has already loaded sysfw	2020-08-11 20:34:46 +05:30
common.h	arm: mach-k3: j7200: Detect if ROM has already loaded sysfw	2020-08-11 20:34:46 +05:30
config_secure.mk	arm: mach-k3: Add secure device build support	2019-04-26 17:51:51 -04:00
config.mk	arm: mach-k3: Fix platform hang when SPL_MULTI_DTB_FIT is not enabled	2020-08-11 20:34:46 +05:30
j721e_init.c	arm: mach-k3: j7200: Detect if ROM has already loaded sysfw	2020-08-11 20:34:46 +05:30
Kconfig	arm: K3: Increase default SYSFW image size allocation	2020-05-11 10:16:49 +05:30
lowlevel_init.S	armv7r: K3: Allow SPL to run only on core 0	2018-11-26 22:52:11 -05:00
Makefile	arm: mach-k3: Clean non-coherent lines out of L3 cache	2020-08-11 10:18:27 +05:30
r5_mpu.c	armv7R: K3: r5_mpu: Enable execute permission for MCU0 BTCM	2020-03-03 13:08:14 +05:30
security.c	common: Drop log.h from common header	2020-05-18 21:19:18 -04:00
sysfw-loader.c	arm: mach-k3: sysfw-loader: Add support for rom loading sysfw image	2020-08-11 20:34:46 +05:30