armv7r: K3: Allow SPL to run only on core 0

Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.

If efuse settings are in lockstep mode: ROM release R5 cores
and SPL continues to run on the R5 core is lockstep mode.

If efuse settings are in split mode: ROM releases both the R5
cores simultaneously and allow SPL to run on both the cores.
In this case it is bootloader's responsibility to detect core
1 and park it. Else both the core will be running bootloader
independently which might result in an unexpected behaviour.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

arch/arm/mach-k3/Makefile

@@ -5,5 +5,5 @@
 
 obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
 obj-$(CONFIG_ARM64) += arm64-mmu.o
-obj-$(CONFIG_CPU_V7R) += r5_mpu.o
+obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
 obj-y += common.o

arch/arm/mach-k3/lowlevel_init.S

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *	Lokesh Vutla <lokeshvutla@ti.com>
+ */
+
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+
+	mrc	p15, 0, r0, c0, c0, 5		@ Read MPIDR
+	and	r0, #0xff
+	cmp	r0, #0x0
+	bne	park_cpu
+	bx	lr
+park_cpu:
+	wfi
+	b	park_cpu
+
+ENDPROC(lowlevel_init)

include/configs/am65x_evm.h

@@ -29,7 +29,9 @@
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME	"tispl.bin"
 #endif
 
+#ifndef CONFIG_CPU_V7R
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
 
 #define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SPL_TEXT_BASE +	\