Lukas Auer 862e2e75e8 riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I ... RISC-V defines the base integer instruction sets as RV32I and RV64I. Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to match this convention. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>		2018-11-26 13:57:29 +08:00
..
arc	emdk->emsdp: Rename board	2018-11-01 23:04:05 +03:00
arm	misc: Update read() and write() methods to return bytes xfered	2018-11-20 19:14:22 -07:00
m68k	m68k: ColdFire mcf5441x, add eSDHC support	2018-09-16 00:01:13 +02:00
microblaze	arch: types.h: factor out fixed width typedefs to int-ll64.h	2018-09-10 20:48:16 -04:00
mips	MIPS: drop asm/const.h	2018-11-20 13:08:15 +01:00
nds32	Kbuild: add LDFLAGS_STANDALONE	2018-11-18 16:02:23 +01:00
nios2	.gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore	2018-06-18 14:43:12 -04:00
powerpc	powerpc: t1040: Correct RCW EC2 settings	2018-10-29 13:19:43 -07:00
riscv	riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I	2018-11-26 13:57:29 +08:00
sandbox	sf: Add a method to obtain the block-protect setting	2018-11-20 19:14:22 -07:00
sh	Kbuild: add LDFLAGS_STANDALONE	2018-11-18 16:02:23 +01:00
x86	cpu: Add DM_FLAG_PRE_RELOC flag to various cpu drivers	2018-11-14 09:16:28 -08:00
xtensa	xtensa: use asm-generic/atomic.h	2018-09-25 21:49:18 -04:00
.gitignore
Kconfig	test: dm: virtio: Add test cases for virtio uclass	2018-11-14 09:16:28 -08:00