mirror of
https://github.com/brain-hackers/u-boot-brain
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a0bda1dd83
Commit e71b6f6622 ("i2c: designware_i2c: Rewrite timing calculation")
change the hcnt and lcnt timing calculation. New timing calculation is
based on calculation from Designware i2c databook.
After this new timing calculation, hcnt will have negative value
with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.
This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall
time used in Designware i2c driver) for Uboot.
Before the fix:
=> i2c dev 0
Setting bus to 0
Failure changing bus number (-22)
After the fix:
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
75 lines
984 B
Plaintext
75 lines
984 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot additions
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*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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* Copyright (c) 2018 Simon Goldschmidt
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*/
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#include "socfpga-common-u-boot.dtsi"
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/{
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aliases {
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spi0 = "/soc/spi@ff705000";
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udc0 = &usb1;
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};
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};
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&can0 {
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status = "okay";
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};
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&watchdog0 {
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status = "disabled";
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};
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&mmc {
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u-boot,dm-pre-reloc;
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};
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&qspi {
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u-boot,dm-pre-reloc;
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};
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&flash0 {
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compatible = "n25q00", "jedec,spi-nor";
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u-boot,dm-pre-reloc;
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partition@qspi-boot {
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/* 8MB for raw data. */
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label = "Flash 0 Raw Data";
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reg = <0x0 0x800000>;
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};
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partition@qspi-rootfs {
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/* 120MB for jffs2 data. */
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label = "Flash 0 jffs2 Filesystem";
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reg = <0x800000 0x7800000>;
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};
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};
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&uart0 {
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clock-frequency = <100000000>;
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u-boot,dm-pre-reloc;
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};
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&uart1 {
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clock-frequency = <100000000>;
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};
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&porta {
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bank-name = "porta";
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};
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&portb {
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bank-name = "portb";
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};
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&portc {
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bank-name = "portc";
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};
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&i2c0 {
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i2c-scl-falling-time-ns = <300>;
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};
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