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arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns

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Commit e71b6f6622 ("i2c: designware_i2c: Rewrite timing calculation")
change the hcnt and lcnt timing calculation. New timing calculation is
based on calculation from Designware i2c databook.

After this new timing calculation, hcnt will have negative value
with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.

This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall
time used in Designware i2c driver) for Uboot.

Before the fix:
=> i2c dev 0
Setting bus to 0
Failure changing bus number (-22)

After the fix:
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Ley Foon Tan 2020-06-10 13:24:16 +08:00 committed by Marek Vasut
parent be79009f3b
commit a0bda1dd83
1 changed files with 4 additions and 0 deletions
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4
arch/arm/dts/socfpga_cyclone5_socdk-u-boot.dtsi
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@ -68,3 +68,7 @@
&portc {
bank-name = "portc";
};
&i2c0 {
i2c-scl-falling-time-ns = <300>;
};