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https://github.com/brain-hackers/u-boot-brain
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74f04490f2
Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed. This patch adds DPAA2 networking support for the following protocols on each SERDES block: * SD #1: 3, 7, 19, 20 * SD #2: 11 Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy-connection-type and phy-handle are added. Top DTS files are also added for each combination of protocol on the 3 SERDES blocks. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
101 lines
1.7 KiB
Plaintext
101 lines
1.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7
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*
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* Some assumptions are made:
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* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
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* * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10)
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*
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* Copyright 2020 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac3 {
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status = "okay";
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phy-handle = <&aquantia_phy1>;
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phy-connection-type = "usxgmii";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&aquantia_phy2>;
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phy-connection-type = "usxgmii";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&aquantia_phy3>;
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phy-connection-type = "usxgmii";
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};
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&dpmac6 {
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status = "okay";
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phy-handle = <&aquantia_phy4>;
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phy-connection-type = "usxgmii";
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};
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&dpmac7 {
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status = "okay";
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phy-handle = <&sgmii_phy1>;
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phy-connection-type = "sgmii";
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};
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&dpmac8 {
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status = "okay";
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phy-handle = <&sgmii_phy2>;
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phy-connection-type = "sgmii";
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};
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&dpmac9 {
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status = "okay";
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phy-handle = <&sgmii_phy3>;
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phy-connection-type = "sgmii";
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};
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&dpmac10 {
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status = "okay";
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phy-handle = <&sgmii_phy4>;
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phy-connection-type = "sgmii";
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};
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&emdio1_slot1 {
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aquantia_phy1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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aquantia_phy2: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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aquantia_phy3: ethernet-phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x2>;
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};
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aquantia_phy4: ethernet-phy@7 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x3>;
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};
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};
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&emdio1_slot2 {
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sgmii_phy1: ethernet-phy@1c {
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reg = <0x1c>;
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};
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sgmii_phy2: ethernet-phy@1d {
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reg = <0x1d>;
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};
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sgmii_phy3: ethernet-phy@1e {
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reg = <0x1e>;
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};
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sgmii_phy4: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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