Patrick Delaunay bb7288ef1c stm32mp1: psci: add synchronization with ROM code ... Use SGI0 interruption and TAMP_BACKUP_MAGIC_NUMBER to synchronize the core1 boot sequence requested by core0 in psci_cpu_on(): - a initial interruption is needed in ROM code after RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off) - the ROM code set to 0 the 2 registers + TAMP_BACKUP_BRANCH_ADDRESS + TAMP_BACKUP_MAGIC_NUMBER when magic is not egual to BOOT_API_A7_CORE0_MAGIC_NUMBER This patch solve issue for cpu1 restart in kernel. echo 0 > /sys/devices/system/cpu/cpu1/online echo 1 > /sys/devices/system/cpu/cpu1/online Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>		2019-05-23 11:36:46 +02:00
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include/mach	stm32mp1: bsec: use device tree new compatible	2019-04-12 16:09:13 +02:00
bsec.c	stm32mp1: cosmetic: bsec: reorder include files	2019-05-23 11:36:46 +02:00
cmd_poweroff.c	stm32mp1: add command poweroff	2019-04-12 16:09:13 +02:00
config.mk	stm32mp1: add trusted boot with TF-A	2019-04-12 16:09:13 +02:00
cpu.c	stm32mp1: Replace OTP read by SHADOW read	2019-04-12 16:09:13 +02:00
dram_init.c	SPDX: Convert all of our multiple license tags to Linux Kernel style	2018-05-07 10:24:31 -04:00
Kconfig	stm32mp1: Move ENV_SIZE and ENV_OFFSET to Kconfig	2019-05-23 11:36:46 +02:00
Makefile	stm32mp1: add command poweroff	2019-04-12 16:09:13 +02:00
psci.c	stm32mp1: psci: add synchronization with ROM code	2019-05-23 11:36:46 +02:00
pwr_regulator.c	stm32mp: regulator: add SoC pwr regulator support	2018-05-08 09:07:38 -04:00
spl.c	stm32mp1: spl: hang with trace when DDR init failed	2019-04-12 16:09:13 +02:00
syscon.c	stm32mp1: add some syscon drivers for syscfg and etpzc	2019-04-12 16:09:13 +02:00