Valentin Longchamp 7e157b0ade mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it ... If the DDR3 module supports industrial temperature range and requires the x2 refresh rate for that temp range, the refresh period must be 3.9us instead of 7.8 us. This was successfuly tested on kmp204x board with some MT41K128M16 DDR3 RAM chips (no module used, chips directly soldered on board with an SPD EEPROM). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix minor conflicts in fsl_ddr_dimm_params.h, lc_common_dimm_params.c, common_timing_params.h] Acked-by: York Sun <yorksun@freescale.com>		2013-10-24 09:35:52 -07:00
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74xx_7xx	Coding Style cleanup: remove trailing white space	2013-10-14 16:06:53 -04:00
mpc5xx	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
mpc5xxx	usb: add enum usb_init_type parameter to usb_lowlevel_init	2013-10-20 23:45:26 +02:00
mpc8xx	Coding Style cleanup: remove trailing white space	2013-10-14 16:06:53 -04:00
mpc8xxx	mpc8xxx: set x2 DDR3 refresh rate if SPD config requires it	2013-10-24 09:35:52 -07:00
mpc83xx	powerpc/usb:Differentiate USB controller base address	2013-10-24 09:35:09 -07:00
mpc85xx	powerpc/mpc85xx: Add workaround for erratum A006379	2013-10-16 16:15:17 -07:00
mpc86xx	Coding Style cleanup: remove trailing white space	2013-10-14 16:06:53 -04:00
mpc512x	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
mpc824x	Coding Style cleanup: remove trailing white space	2013-10-14 16:06:53 -04:00
mpc8260	Coding Style cleanup: remove trailing white space	2013-10-14 16:06:53 -04:00
ppc4xx	usb: add enum usb_init_type parameter to usb_lowlevel_init	2013-10-20 23:45:26 +02:00