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7ce6c8ae58
u-boot-brain/arch/arm/mach-k3
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Vignesh Raghavendra 7ce6c8ae58 arm: mach-k3: Add HyperFlash boot mode support 
HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-09-15 18:51:52 +05:30
..
include/mach arm: mach-k3: Add HyperFlash boot mode support 2020-09-15 18:51:52 +05:30
am6_init.c arm: mach-k3: sysfw-loader: Add support for rom loading sysfw image 2020-08-11 20:34:46 +05:30
arm64-mmu.c armv8: K3: j721e: Add DSP internal memory regions in MMU table 2020-03-16 12:32:47 +05:30
cache.S arm: mach-k3: Clean non-coherent lines out of L3 cache 2020-08-11 10:18:27 +05:30
common.c arm: mach-k3: j7200: Detect if ROM has already loaded sysfw 2020-08-11 20:34:46 +05:30
common.h arm: mach-k3: j7200: Detect if ROM has already loaded sysfw 2020-08-11 20:34:46 +05:30
config_secure.mk arm: mach-k3: Add secure device build support 2019-04-26 17:51:51 -04:00
config.mk arm: mach-k3: Fix platform hang when SPL_MULTI_DTB_FIT is not enabled 2020-08-11 20:34:46 +05:30
j721e_init.c arm: mach-k3: j7200: Detect if ROM has already loaded sysfw 2020-08-11 20:34:46 +05:30
Kconfig arm: K3: Increase default SYSFW image size allocation 2020-05-11 10:16:49 +05:30
lowlevel_init.S armv7r: K3: Allow SPL to run only on core 0 2018-11-26 22:52:11 -05:00
Makefile arm: mach-k3: Clean non-coherent lines out of L3 cache 2020-08-11 10:18:27 +05:30
r5_mpu.c armv7R: K3: r5_mpu: Enable execute permission for MCU0 BTCM 2020-03-03 13:08:14 +05:30
security.c common: Drop log.h from common header 2020-05-18 21:19:18 -04:00
sysfw-loader.c arm: mach-k3: sysfw-loader: Add support for rom loading sysfw image 2020-08-11 20:34:46 +05:30