Michal Simek 7ba69b7dcc arm: zynq: Fix timer loadaddress ... Reload address was written to the counter register instead of load register. The problem happens when timer expires but never reload to ~0UL (it is downcount timer). Reported-by: Stephen MacMahon <stephenm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2013-09-23 16:26:32 +02:00
..
arm_intcm	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
arm720t	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
arm920t	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
arm925t	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
arm926ejs	Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'	2013-09-05 11:15:26 +02:00
arm946es	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
arm1136	ARM: omap24xx: remove remainders of dead board	2013-08-15 18:38:33 -04:00
arm1176	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
armv7	arm: zynq: Fix timer loadaddress	2013-09-23 16:26:32 +02:00
ixp	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
pxa	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
sa1100	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
tegra-common	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
tegra20-common	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
tegra30-common	Tegra114: Initialize System Counter (TSC) with osc frequency	2013-04-15 11:01:38 -07:00
tegra114-common	Tegra114: Initialize System Counter (TSC) with osc frequency	2013-04-15 11:01:38 -07:00
u-boot-spl.lds	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
u-boot.lds	arm: lds: Remove libgcc eabi exception handling tables	2013-09-05 13:41:42 +02:00