Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'
Conflicts: drivers/serial/serial.c The conflict above was a trivial case of adding one init function in each branch, and manually resolved in merge.
This commit is contained in:
Albert ARIBAUD
commit
19d829fa60
|
|
@ -0,0 +1,6 @@
|
|||
SECTION 0x0 BOOTABLE
|
||||
TAG LAST
|
||||
LOAD 0x0 spl/u-boot-spl.bin
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||||
CALL 0x14 0x0
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||||
LOAD 0x40000100 u-boot.bin
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||||
CALL 0x40000100 0x0
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||||
|
|
@ -0,0 +1,8 @@
|
|||
SECTION 0x0 BOOTABLE
|
||||
TAG LAST
|
||||
LOAD 0x0 spl/u-boot-spl.bin
|
||||
LOAD IVT 0x8000 0x14
|
||||
CALL HAB 0x8000 0x0
|
||||
LOAD 0x40000100 u-boot.bin
|
||||
LOAD IVT 0x8000 0x40000100
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||||
CALL HAB 0x8000 0x0
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|
|
@ -36,7 +36,7 @@ static void mxs_power_clock2pll(void)
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CLKCTRL_CLKSEQ_BYPASS_CPU);
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}
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|
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static void mxs_power_clear_auto_restart(void)
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static void mxs_power_set_auto_restart(void)
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{
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struct mxs_rtc_regs *rtc_regs =
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(struct mxs_rtc_regs *)MXS_RTC_BASE;
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|
|
@ -49,10 +49,7 @@ static void mxs_power_clear_auto_restart(void)
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while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
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;
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|
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/*
|
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* Due to the hardware design bug of mx28 EVK-A
|
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* we need to set the AUTO_RESTART bit.
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*/
|
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/* Do nothing if flag already set */
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if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
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return;
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|
|
@ -911,7 +908,7 @@ void mxs_power_init(void)
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mxs_ungate_power();
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mxs_power_clock2xtal();
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mxs_power_clear_auto_restart();
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mxs_power_set_auto_restart();
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mxs_power_set_linreg();
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mxs_power_setup_5v_detect();
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|
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|
|
|
|||
|
|
@ -11,10 +11,11 @@ include $(TOPDIR)/config.mk
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|
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LIB = $(obj)lib$(SOC).o
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COBJS = soc.o clock.o
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COBJS-y = soc.o clock.o
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COBJS-$(CONFIG_SECURE_BOOT) += hab.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
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all: $(obj).depend $(LIB)
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|
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|
|
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|
|
@ -0,0 +1,104 @@
|
|||
/*
|
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* Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
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*
|
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* SPDX-License-Identifier: GPL-2.0+
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*/
|
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|
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/hab.h>
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|
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/* -------- start of HAB API updates ------------*/
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#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)
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#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)
|
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#define hab_rvt_authenticate_image \
|
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((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)
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#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY)
|
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#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT)
|
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#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT
|
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|
||||
bool is_hab_enabled(void)
|
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{
|
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
|
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struct fuse_bank *bank = &ocotp->bank[0];
|
||||
struct fuse_bank0_regs *fuse =
|
||||
(struct fuse_bank0_regs *)bank->fuse_regs;
|
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uint32_t reg = readl(&fuse->cfg5);
|
||||
|
||||
return (reg & 0x2) == 0x2;
|
||||
}
|
||||
|
||||
void display_event(uint8_t *event_data, size_t bytes)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
if (!(event_data && bytes > 0))
|
||||
return;
|
||||
|
||||
for (i = 0; i < bytes; i++) {
|
||||
if (i == 0)
|
||||
printf("\t0x%02x", event_data[i]);
|
||||
else if ((i % 8) == 0)
|
||||
printf("\n\t0x%02x", event_data[i]);
|
||||
else
|
||||
printf(" 0x%02x", event_data[i]);
|
||||
}
|
||||
}
|
||||
|
||||
int get_hab_status(void)
|
||||
{
|
||||
uint32_t index = 0; /* Loop index */
|
||||
uint8_t event_data[128]; /* Event data buffer */
|
||||
size_t bytes = sizeof(event_data); /* Event size in bytes */
|
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enum hab_config config = 0;
|
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enum hab_state state = 0;
|
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|
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if (is_hab_enabled())
|
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puts("\nSecure boot enabled\n");
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else
|
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puts("\nSecure boot disabled\n");
|
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|
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/* Check HAB status */
|
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if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
|
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printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
|
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config, state);
|
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|
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/* Display HAB Error events */
|
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while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
|
||||
&bytes) == HAB_SUCCESS) {
|
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puts("\n");
|
||||
printf("--------- HAB Event %d -----------------\n",
|
||||
index + 1);
|
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puts("event data:\n");
|
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display_event(event_data, bytes);
|
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puts("\n");
|
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bytes = sizeof(event_data);
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index++;
|
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}
|
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}
|
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/* Display message if no HAB events are found */
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else {
|
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printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
|
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config, state);
|
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puts("No HAB Events Found!\n\n");
|
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}
|
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return 0;
|
||||
}
|
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|
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int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
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{
|
||||
if ((argc != 1)) {
|
||||
cmd_usage(cmdtp);
|
||||
return 1;
|
||||
}
|
||||
|
||||
get_hab_status();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
|
||||
"display HAB status",
|
||||
""
|
||||
);
|
||||
|
|
@ -213,6 +213,34 @@ const struct boot_mode soc_boot_modes[] = {
|
|||
|
||||
void s_init(void)
|
||||
{
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
int is_6q = is_cpu_type(MXC_CPU_MX6Q);
|
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u32 mask480;
|
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u32 mask528;
|
||||
|
||||
/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
|
||||
* to make sure PFD is working right, otherwise, PFDs may
|
||||
* not output clock after reset, MX6DL and MX6SL have added 396M pfd
|
||||
* workaround in ROM code, as bus clock need it
|
||||
*/
|
||||
|
||||
mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
|
||||
ANATOP_PFD_CLKGATE_MASK(1) |
|
||||
ANATOP_PFD_CLKGATE_MASK(2) |
|
||||
ANATOP_PFD_CLKGATE_MASK(3);
|
||||
mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
|
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ANATOP_PFD_CLKGATE_MASK(1) |
|
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ANATOP_PFD_CLKGATE_MASK(3);
|
||||
|
||||
/*
|
||||
* Don't reset PFD2 on DL/S
|
||||
*/
|
||||
if (is_6q)
|
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mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
|
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writel(mask480, &anatop->pfd_480_set);
|
||||
writel(mask528, &anatop->pfd_528_set);
|
||||
writel(mask480, &anatop->pfd_480_clr);
|
||||
writel(mask528, &anatop->pfd_528_clr);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IMX_HDMI
|
||||
|
|
|
|||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SECURE_MX6Q_H__
|
||||
#define __SECURE_MX6Q_H__
|
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|
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#include <linux/types.h>
|
||||
|
||||
/* -------- start of HAB API updates ------------*/
|
||||
/* The following are taken from HAB4 SIS */
|
||||
|
||||
/* Status definitions */
|
||||
enum hab_status {
|
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HAB_STS_ANY = 0x00,
|
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HAB_FAILURE = 0x33,
|
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HAB_WARNING = 0x69,
|
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HAB_SUCCESS = 0xf0
|
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};
|
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|
||||
/* Security Configuration definitions */
|
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enum hab_config {
|
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HAB_CFG_RETURN = 0x33, /**< Field Return IC */
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HAB_CFG_OPEN = 0xf0, /**< Non-secure IC */
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HAB_CFG_CLOSED = 0xcc /**< Secure IC */
|
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};
|
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|
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/* State definitions */
|
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enum hab_state {
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HAB_STATE_INITIAL = 0x33, /**< Initialising state (transitory) */
|
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HAB_STATE_CHECK = 0x55, /**< Check state (non-secure) */
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HAB_STATE_NONSECURE = 0x66, /**< Non-secure state */
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HAB_STATE_TRUSTED = 0x99, /**< Trusted state */
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HAB_STATE_SECURE = 0xaa, /**< Secure state */
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HAB_STATE_FAIL_SOFT = 0xcc, /**< Soft fail state */
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HAB_STATE_FAIL_HARD = 0xff, /**< Hard fail state (terminal) */
|
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HAB_STATE_NONE = 0xf0, /**< No security state machine */
|
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HAB_STATE_MAX
|
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};
|
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|
||||
/*Function prototype description*/
|
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typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t,
|
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uint8_t* , size_t*);
|
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typedef enum hab_status hab_rvt_report_status_t(enum hab_config *,
|
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enum hab_state *);
|
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typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*);
|
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typedef enum hab_status hab_rvt_entry_t(void);
|
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typedef enum hab_status hab_rvt_exit_t(void);
|
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typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
|
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void **, size_t *, hab_loader_callback_f_t);
|
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typedef void hapi_clock_init_t(void);
|
||||
|
||||
#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
|
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#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
|
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#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
|
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#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
|
||||
#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
|
||||
#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
|
||||
|
||||
#define HAB_CID_ROM 0 /**< ROM Caller ID */
|
||||
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
|
||||
/* ----------- end of HAB API updates ------------*/
|
||||
|
||||
#endif
|
||||
|
|
@ -456,7 +456,13 @@ struct fuse_bank0_regs {
|
|||
u32 uid_low;
|
||||
u32 rsvd1[3];
|
||||
u32 uid_high;
|
||||
u32 rsvd2[0x17];
|
||||
u32 rsvd2[3];
|
||||
u32 rsvd3[4];
|
||||
u32 rsvd4[4];
|
||||
u32 rsvd5[4];
|
||||
u32 cfg5;
|
||||
u32 rsvd6[3];
|
||||
u32 rsvd7[4];
|
||||
};
|
||||
|
||||
struct fuse_bank4_regs {
|
||||
|
|
@ -629,29 +635,12 @@ struct anatop_regs {
|
|||
u32 digprog_sololite; /* 0x280 */
|
||||
};
|
||||
|
||||
#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
|
||||
#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
|
||||
#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
|
||||
#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
|
||||
#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
|
||||
#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
|
||||
#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
|
||||
#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
|
||||
#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
|
||||
#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
|
||||
#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
|
||||
#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
|
||||
#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
|
||||
#define ANATOP_PFD_FRAC_SHIFT(n) ((n)*8)
|
||||
#define ANATOP_PFD_FRAC_MASK(n) (0x3f<<ANATOP_PFD_FRAC_SHIFT(n))
|
||||
#define ANATOP_PFD_STABLE_SHIFT(n) (6+((n)*8))
|
||||
#define ANATOP_PFD_STABLE_MASK(n) (1<<ANATOP_PFD_STABLE_SHIFT(n))
|
||||
#define ANATOP_PFD_CLKGATE_SHIFT(n) (7+((n)*8))
|
||||
#define ANATOP_PFD_CLKGATE_MASK(n) (1<<ANATOP_PFD_CLKGATE_SHIFT(n))
|
||||
|
||||
struct iomuxc_base_regs {
|
||||
u32 gpr[14]; /* 0x000 */
|
||||
|
|
|
|||
|
|
@ -19,6 +19,13 @@
|
|||
|
||||
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
|
||||
u32 get_cpu_rev(void);
|
||||
|
||||
/* returns MXC_CPU_ value */
|
||||
#define cpu_type(rev) (((rev) >> 12)&0xff)
|
||||
|
||||
/* use with MXC_CPU_ constants */
|
||||
#define is_cpu_type(cpu) (cpu_type(get_cpu_rev()) == cpu)
|
||||
|
||||
const char *get_imx_type(u32 imxtype);
|
||||
unsigned imx_ddr_size(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Freescale MXS UARTAPP Register Definitions
|
||||
*
|
||||
* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
|
||||
*
|
||||
* Based on code from LTIB:
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM___MXS_UARTAPP_H
|
||||
#define __ARCH_ARM___MXS_UARTAPP_H
|
||||
|
||||
#include <asm/imx-common/regs-common.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct mxs_uartapp_regs {
|
||||
mxs_reg_32(hw_uartapp_ctrl0)
|
||||
mxs_reg_32(hw_uartapp_ctrl1)
|
||||
mxs_reg_32(hw_uartapp_ctrl2)
|
||||
mxs_reg_32(hw_uartapp_linectrl)
|
||||
mxs_reg_32(hw_uartapp_linectrl2)
|
||||
mxs_reg_32(hw_uartapp_intr)
|
||||
mxs_reg_32(hw_uartapp_data)
|
||||
mxs_reg_32(hw_uartapp_stat)
|
||||
mxs_reg_32(hw_uartapp_debug)
|
||||
mxs_reg_32(hw_uartapp_version)
|
||||
mxs_reg_32(hw_uartapp_autobaud)
|
||||
};
|
||||
#endif
|
||||
|
||||
#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31)
|
||||
#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30)
|
||||
#define UARTAPP_CTRL0_RUN_MASK (1 << 29)
|
||||
#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28)
|
||||
#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27)
|
||||
#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16
|
||||
#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16)
|
||||
#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0
|
||||
#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_CTRL1_RUN_MASK (1 << 28)
|
||||
|
||||
#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0
|
||||
#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31)
|
||||
#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30)
|
||||
#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29)
|
||||
#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28)
|
||||
#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27)
|
||||
#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26)
|
||||
#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25)
|
||||
#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20)
|
||||
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20)
|
||||
#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16)
|
||||
#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16)
|
||||
#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15)
|
||||
#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14)
|
||||
#define UARTAPP_CTRL2_OUT2_MASK (1 << 13)
|
||||
#define UARTAPP_CTRL2_OUT1_MASK (1 << 12)
|
||||
#define UARTAPP_CTRL2_RTS_MASK (1 << 11)
|
||||
#define UARTAPP_CTRL2_DTR_MASK (1 << 10)
|
||||
#define UARTAPP_CTRL2_RXE_MASK (1 << 9)
|
||||
#define UARTAPP_CTRL2_TXE_MASK (1 << 8)
|
||||
#define UARTAPP_CTRL2_LBE_MASK (1 << 7)
|
||||
#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6)
|
||||
|
||||
#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2)
|
||||
#define UARTAPP_CTRL2_SIREN_MASK (1 << 1)
|
||||
#define UARTAPP_CTRL2_UARTEN_MASK 0x01
|
||||
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16)
|
||||
#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6
|
||||
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8
|
||||
#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8)
|
||||
#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
|
||||
|
||||
#define UARTAPP_LINECTRL_SPS_MASK (1 << 7)
|
||||
#define UARTAPP_LINECTRL_WLEN_OFFSET 5
|
||||
#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5)
|
||||
#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5)
|
||||
|
||||
#define UARTAPP_LINECTRL_FEN_MASK (1 << 4)
|
||||
#define UARTAPP_LINECTRL_STP2_MASK (1 << 3)
|
||||
#define UARTAPP_LINECTRL_EPS_MASK (1 << 2)
|
||||
#define UARTAPP_LINECTRL_PEN_MASK (1 << 1)
|
||||
#define UARTAPP_LINECTRL_BRK_MASK 1
|
||||
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16)
|
||||
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6
|
||||
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8
|
||||
#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8)
|
||||
#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F
|
||||
|
||||
#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7)
|
||||
#define UARTAPP_LINECTRL2_WLEN_OFFSET 5
|
||||
#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5)
|
||||
#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5)
|
||||
|
||||
#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4)
|
||||
#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3)
|
||||
#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2)
|
||||
#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1)
|
||||
|
||||
#define UARTAPP_INTR_ABDIEN_MASK (1 << 27)
|
||||
#define UARTAPP_INTR_OEIEN_MASK (1 << 26)
|
||||
#define UARTAPP_INTR_BEIEN_MASK (1 << 25)
|
||||
#define UARTAPP_INTR_PEIEN_MASK (1 << 24)
|
||||
#define UARTAPP_INTR_FEIEN_MASK (1 << 23)
|
||||
#define UARTAPP_INTR_RTIEN_MASK (1 << 22)
|
||||
#define UARTAPP_INTR_TXIEN_MASK (1 << 21)
|
||||
#define UARTAPP_INTR_RXIEN_MASK (1 << 20)
|
||||
#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19)
|
||||
#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18)
|
||||
#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17)
|
||||
#define UARTAPP_INTR_RIMIEN_MASK (1 << 16)
|
||||
|
||||
#define UARTAPP_INTR_ABDIS_MASK (1 << 11)
|
||||
#define UARTAPP_INTR_OEIS_MASK (1 << 10)
|
||||
#define UARTAPP_INTR_BEIS_MASK (1 << 9)
|
||||
#define UARTAPP_INTR_PEIS_MASK (1 << 8)
|
||||
#define UARTAPP_INTR_FEIS_MASK (1 << 7)
|
||||
#define UARTAPP_INTR_RTIS_MASK (1 << 6)
|
||||
#define UARTAPP_INTR_TXIS_MASK (1 << 5)
|
||||
#define UARTAPP_INTR_RXIS_MASK (1 << 4)
|
||||
#define UARTAPP_INTR_DSRMIS_MASK (1 << 3)
|
||||
#define UARTAPP_INTR_DCDMIS_MASK (1 << 2)
|
||||
#define UARTAPP_INTR_CTSMIS_MASK (1 << 1)
|
||||
#define UARTAPP_INTR_RIMIS_MASK 0x1
|
||||
|
||||
#define UARTAPP_DATA_DATA_OFFSET 0
|
||||
#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF
|
||||
#define UARTAPP_STAT_PRESENT_MASK (1 << 31)
|
||||
#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31)
|
||||
#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31)
|
||||
|
||||
#define UARTAPP_STAT_HISPEED_MASK (1 << 30)
|
||||
#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30)
|
||||
#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30)
|
||||
|
||||
#define UARTAPP_STAT_BUSY_MASK (1 << 29)
|
||||
#define UARTAPP_STAT_CTS_MASK (1 << 28)
|
||||
#define UARTAPP_STAT_TXFE_MASK (1 << 27)
|
||||
#define UARTAPP_STAT_RXFF_MASK (1 << 26)
|
||||
#define UARTAPP_STAT_TXFF_MASK (1 << 25)
|
||||
#define UARTAPP_STAT_RXFE_MASK (1 << 24)
|
||||
#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20
|
||||
#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20)
|
||||
|
||||
#define UARTAPP_STAT_OERR_MASK (1 << 19)
|
||||
#define UARTAPP_STAT_BERR_MASK (1 << 18)
|
||||
#define UARTAPP_STAT_PERR_MASK (1 << 17)
|
||||
#define UARTAPP_STAT_FERR_MASK (1 << 16)
|
||||
#define UARTAPP_STAT_RXCOUNT_OFFSET 0
|
||||
#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16
|
||||
#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16)
|
||||
|
||||
#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10
|
||||
#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10)
|
||||
|
||||
#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5)
|
||||
#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4)
|
||||
#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3)
|
||||
#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2)
|
||||
#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1)
|
||||
#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01
|
||||
|
||||
#define UARTAPP_VERSION_MAJOR_OFFSET 24
|
||||
#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24)
|
||||
|
||||
#define UARTAPP_VERSION_MINOR_OFFSET 16
|
||||
#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16)
|
||||
|
||||
#define UARTAPP_VERSION_STEP_OFFSET 0
|
||||
#define UARTAPP_VERSION_STEP_MASK 0xFFFF
|
||||
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24)
|
||||
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16
|
||||
#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16)
|
||||
|
||||
#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4)
|
||||
#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3)
|
||||
#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2)
|
||||
#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1)
|
||||
#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01
|
||||
#endif /* __ARCH_ARM___UARTAPP_H */
|
||||
|
|
@ -622,7 +622,6 @@ int board_video_skip(void)
|
|||
static void setup_display(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
|
||||
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
|
||||
int reg;
|
||||
|
||||
|
|
@ -633,10 +632,6 @@ static void setup_display(void)
|
|||
reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
|
||||
writel(reg, &mxc_ccm->CCGR3);
|
||||
|
||||
/* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
|
||||
writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
|
||||
writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
|
||||
|
||||
/* set LDB0, LDB1 clk select to 011/011 */
|
||||
reg = readl(&mxc_ccm->cs2cdr);
|
||||
reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
|
||||
|
|
@ -666,7 +661,8 @@ static void setup_display(void)
|
|||
writel(reg, &iomux->gpr[2]);
|
||||
|
||||
reg = readl(&iomux->gpr[3]);
|
||||
reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
|
||||
reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
|
||||
|IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
|
||||
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
|
||||
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
|
||||
writel(reg, &iomux->gpr[3]);
|
||||
|
|
|
|||
|
|
@ -7,8 +7,7 @@ Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
|
|||
1. Boot source, boot from SD card
|
||||
---------------------------------
|
||||
|
||||
This version of u-boot works only on the SD card. By default, the
|
||||
Congatec board can boot only from the SPI-NOR.
|
||||
By default, the Congatec board can boot only from the SPI-NOR.
|
||||
But, with the u-boot version provided with the board you can write boot
|
||||
registers to force the board to reboot and boot from the SD slot. If
|
||||
"bmode" command is not available from your pre-installed u-boot, these
|
||||
|
|
|
|||
|
|
@ -204,6 +204,7 @@ mx23evk arm arm926ejs mx23evk freesca
|
|||
m28evk arm arm926ejs m28evk denx mxs m28evk
|
||||
mx28evk arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_MMC
|
||||
mx28evk_nand arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_NAND
|
||||
mx28evk_auart_console arm arm926ejs mx28evk freescale mxs mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC
|
||||
sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs
|
||||
nhk8815 arm arm926ejs nhk8815 st nomadik
|
||||
nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND
|
||||
|
|
|
|||
|
|
@ -135,6 +135,7 @@ static const table_entry_t uimage_type[] = {
|
|||
{ IH_TYPE_SCRIPT, "script", "Script", },
|
||||
{ IH_TYPE_STANDALONE, "standalone", "Standalone Program", },
|
||||
{ IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",},
|
||||
{ IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",},
|
||||
{ -1, "", "", },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -220,6 +220,15 @@ LDFLAGS_FINAL += --gc-sections
|
|||
endif
|
||||
|
||||
# TODO(sjg@chromium.org): Is this correct on Mac OS?
|
||||
|
||||
# MXSImage needs LibSSL
|
||||
ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
|
||||
HOSTLIBS += -lssl -lcrypto
|
||||
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
|
||||
# the mxsimage support within tools/mxsimage.c .
|
||||
HOSTCFLAGS += -DCONFIG_MXS
|
||||
endif
|
||||
|
||||
ifdef CONFIG_FIT_SIGNATURE
|
||||
HOSTLIBS += -lssl -lcrypto
|
||||
|
||||
|
|
|
|||
|
|
@ -15,9 +15,6 @@ Booting from NOR flash does not require to use this image type.
|
|||
For more details refer Chapter 2 - System Boot and section 2.14
|
||||
(flash header description) of the processor's manual.
|
||||
|
||||
This implementation does not use at the moment the secure boot feature
|
||||
of the processor. The image is generated disabling all security fields.
|
||||
|
||||
Command syntax:
|
||||
--------------
|
||||
./tools/mkimage -l <mx u-boot_file>
|
||||
|
|
@ -86,6 +83,33 @@ Configuration command line syntax:
|
|||
Example:
|
||||
BOOT_FROM spi
|
||||
|
||||
CSF value
|
||||
|
||||
Total size of CSF (Command Sequence File)
|
||||
used for Secure Boot/ High Assurance Boot
|
||||
(HAB).
|
||||
|
||||
Using this command will populate the IVT
|
||||
(Initial Vector Table) CSF pointer and adjust
|
||||
the length fields only. The CSF itself needs
|
||||
to be generated with Freescale tools and
|
||||
'manually' appended to the u-boot.imx file.
|
||||
|
||||
The CSF is then simply concatenated
|
||||
to the u-boot image, making a signed bootloader,
|
||||
that the processor can verify
|
||||
if the fuses for the keys are burned.
|
||||
|
||||
Further infos how to configure the SOC to verify
|
||||
the bootloader can be found in the "High
|
||||
Assurance Boot Version Application Programming
|
||||
Interface Reference Manual" as part of the
|
||||
Freescale Code Signing Tool, available on the
|
||||
manufacturer's website.
|
||||
|
||||
Example:
|
||||
CSF 0x2000
|
||||
|
||||
DATA type address value
|
||||
|
||||
type: word=4, halfword=2, byte=1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,48 @@
|
|||
High Assurance Boot (HAB) for i.MX6 CPUs
|
||||
|
||||
To authenticate U-Boot only by the CPU there is no code required in
|
||||
U-Boot itself. However, the U-Boot image to be programmed into the
|
||||
boot media needs to be properly constructed, i.e. it must contain a
|
||||
proper Command Sequence File (CSF).
|
||||
|
||||
The Initial Vector Table contains a pointer to the CSF. Please see
|
||||
doc/README.imximage for how to prepare u-boot.imx.
|
||||
|
||||
The CSF itself is being generated by Freescale HAB tools.
|
||||
|
||||
mkimage will output additional information about "HAB Blocks"
|
||||
which can be used in the Freescale tooling to authenticate U-Boot
|
||||
(entries in the CSF file).
|
||||
|
||||
Image Type: Freescale IMX Boot Image
|
||||
Image Ver: 2 (i.MX53/6 compatible)
|
||||
Data Size: 327680 Bytes = 320.00 kB = 0.31 MB
|
||||
Load Address: 177ff420
|
||||
Entry Point: 17800000
|
||||
HAB Blocks: 177ff400 00000000 0004dc00
|
||||
^^^^^^^^ ^^^^^^^^ ^^^^^^^^
|
||||
| | |
|
||||
| | -------- (1)
|
||||
| |
|
||||
| ------------------- (2)
|
||||
|
|
||||
--------------------------- (3)
|
||||
|
||||
(1) Size of area in file u-boot.imx to sign
|
||||
This area should include the IVT, the Boot Data the DCD
|
||||
and U-Boot itself.
|
||||
(2) Start of area in u-boot.imx to sign
|
||||
(3) Start of area in RAM to authenticate
|
||||
|
||||
CONFIG_SECURE_BOOT currently enables only an additional command
|
||||
'hab_status' in U-Boot to retrieve the HAB status and events. This
|
||||
can be useful while developing and testing HAB.
|
||||
|
||||
Commands to generate a signed U-Boot using Freescale HAB tools:
|
||||
cst --o U-Boot_CSF.bin < U-Boot.CSF
|
||||
objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0x00 \
|
||||
U-Boot_CSF.bin U-Boot_CSF_pad.bin
|
||||
cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx
|
||||
|
||||
NOTE: U-Boot_CSF.bin needs to be padded to the value specified in
|
||||
the imximage.cfg file.
|
||||
|
|
@ -0,0 +1,165 @@
|
|||
Freescale i.MX233/i.MX28 SB image generator via mkimage
|
||||
=======================================================
|
||||
|
||||
This tool allows user to produce SB BootStream encrypted with a zero key.
|
||||
Such a BootStream is then bootable on i.MX23/i.MX28.
|
||||
|
||||
Usage -- producing image:
|
||||
=========================
|
||||
The mxsimage tool is targeted to be a simple replacement for the elftosb2 .
|
||||
To generate an image, write an image configuration file and run:
|
||||
|
||||
mkimage -A arm -O u-boot -T mxsimage -n <path to configuration file> \
|
||||
<output bootstream file>
|
||||
|
||||
The output bootstream file is usually using the .sb file extension. Note
|
||||
that the example configuration files for producing bootable BootStream with
|
||||
the U-Boot bootloader can be found under arch/arm/boot/cpu/arm926ejs/mxs/
|
||||
directory. See the following files:
|
||||
|
||||
mxsimage.mx23.cfg -- This is an example configuration for i.MX23
|
||||
mxsimage.mx28.cfg -- This is an example configuration for i.MX28
|
||||
|
||||
Each configuration file uses very simple instruction semantics and a few
|
||||
additional rules have to be followed so that a useful image can be produced.
|
||||
These semantics and rules will be outlined now.
|
||||
|
||||
- Each line of the configuration file contains exactly one instruction.
|
||||
- Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 .
|
||||
- The configuration file is a concatenation of blocks called "sections" and
|
||||
optionally "DCD blocks" (see below).
|
||||
- Each "section" is started by the "SECTION" instruction.
|
||||
- The "SECTION" instruction has the following semantics:
|
||||
|
||||
SECTION u32_section_number [BOOTABLE]
|
||||
- u32_section_number :: User-selected ID of the section
|
||||
- BOOTABLE :: Sets the section as bootable
|
||||
|
||||
- A bootable section is one from which the BootROM starts executing
|
||||
subsequent instructions or code. Exactly one section must be selected
|
||||
as bootable, usually the one containing the instructions and data to
|
||||
load the bootloader.
|
||||
|
||||
- A "SECTION" must be immediatelly followed by a "TAG" instruction.
|
||||
- The "TAG" instruction has the following semantics:
|
||||
|
||||
TAG [LAST]
|
||||
- LAST :: Flag denoting the last section in the file
|
||||
|
||||
- After a "TAG" unstruction, any of the following instructions may follow
|
||||
in any order and any quantity:
|
||||
|
||||
NOOP
|
||||
- This instruction does nothing
|
||||
|
||||
LOAD u32_address string_filename
|
||||
- Instructs the BootROM to load file pointed by "string_filename" onto
|
||||
address "u32_address".
|
||||
|
||||
LOAD IVT u32_address u32_IVT_entry_point
|
||||
- Crafts and loads IVT onto address "u32_address" with the entry point
|
||||
of u32_IVT_entry_point.
|
||||
- i.MX28-specific instruction!
|
||||
|
||||
LOAD DCD u32_address u32_DCD_block_ID
|
||||
- Loads the DCD block with ID "u32_DCD_block_ID" onto address
|
||||
"u32_address" and executes the contents of this DCD block
|
||||
- i.MX28-specific instruction!
|
||||
|
||||
FILL u32_address u32_pattern u32_length
|
||||
- Starts to write memory from addres "u32_address" with a pattern
|
||||
specified by "u32_pattern". Writes exactly "u32_length" bytes of the
|
||||
pattern.
|
||||
|
||||
JUMP [HAB] u32_address [u32_r0_arg]
|
||||
- Jumps onto memory address specified by "u32_address" by setting this
|
||||
address in PT. The BootROM will pass the "u32_r0_arg" value in ARM
|
||||
register "r0" to the executed code if this option is specified.
|
||||
Otherwise, ARM register "r0" will default to value 0x00000000. The
|
||||
optional "HAB" flag is i.MX28-specific flag turning on the HAB boot.
|
||||
|
||||
CALL [HAB] u32_address [u32_r0_arg]
|
||||
- See JUMP instruction above, as the operation is exactly the same with
|
||||
one difference. The CALL instruction does allow returning into the
|
||||
BootROM from the executed code. U-Boot makes use of this in it's SPL
|
||||
code.
|
||||
|
||||
MODE string_mode
|
||||
- Restart the CPU and start booting from device specified by the
|
||||
"string_mode" argument. The "string_mode" differs for each CPU
|
||||
and can be:
|
||||
i.MX23, string_mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH
|
||||
JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1
|
||||
i.MX28, string_mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH
|
||||
JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1
|
||||
|
||||
- An optional "DCD" blocks can be added at the begining of the configuration
|
||||
file. Note that the DCD is only supported on i.MX28.
|
||||
- The DCD blocks must be inserted before the first "section" in the
|
||||
configuration file.
|
||||
- The DCD block has the following semantics:
|
||||
|
||||
DCD u32_DCD_block_ID
|
||||
- u32_DCD_block_ID :: The ID number of the DCD block, must match
|
||||
the ID number used by "LOAD DCD" instruction.
|
||||
|
||||
- The DCD block must be followed by one of the following instructions. All
|
||||
of the instructions operate either on 1, 2 or 4 bytes. This is selected by
|
||||
the 'n' suffix of the instruction:
|
||||
|
||||
WRITE.n u32_address u32_value
|
||||
- Write the "u32_value" to the "u32_address" address.
|
||||
|
||||
ORR.n u32_address u32_value
|
||||
- Read the "u32_address", perform a bitwise-OR with the "u32_value" and
|
||||
write the result back to "u32_address".
|
||||
|
||||
ANDC.n u32_address u32_value
|
||||
- Read the "u32_address", perform a bitwise-AND with the complement of
|
||||
"u32_value" and write the result back to "u32_address".
|
||||
|
||||
EQZ.n u32_address u32_count
|
||||
- Read the "u32_address" at most "u32_count" times and test if the value
|
||||
read is zero. If it is, break the loop earlier.
|
||||
|
||||
NEZ.n u32_address u32_count
|
||||
- Read the "u32_address" at most "u32_count" times and test if the value
|
||||
read is non-zero. If it is, break the loop earlier.
|
||||
|
||||
EQ.n u32_address u32_mask
|
||||
- Read the "u32_address" in a loop and test if the result masked with
|
||||
"u32_mask" equals the "u32_mask". If the values are equal, break the
|
||||
reading loop.
|
||||
|
||||
NEQ.n u32_address u32_mask
|
||||
- Read the "u32_address" in a loop and test if the result masked with
|
||||
"u32_mask" does not equal the "u32_mask". If the values are not equal,
|
||||
break the reading loop.
|
||||
|
||||
NOOP
|
||||
- This instruction does nothing.
|
||||
|
||||
- If the verbose output from the BootROM is enabled, the BootROM will produce a
|
||||
letter on the Debug UART for each instruction it started processing. Here is a
|
||||
mapping between the above instructions and the BootROM verbose output:
|
||||
|
||||
H -- SB Image header loaded
|
||||
T -- TAG instruction
|
||||
N -- NOOP instruction
|
||||
L -- LOAD instruction
|
||||
F -- FILL instruction
|
||||
J -- JUMP instruction
|
||||
C -- CALL instruction
|
||||
M -- MODE instruction
|
||||
|
||||
Usage -- verifying image:
|
||||
=========================
|
||||
|
||||
The mxsimage can also verify and dump contents of an image. Use the following
|
||||
syntax to verify and dump contents of an image:
|
||||
|
||||
mkimage -l <input bootstream file>
|
||||
|
||||
This will output all the information from the SB image header and all the
|
||||
instructions contained in the SB image. It will also check if the various
|
||||
checksums in the SB image are correct.
|
||||
|
|
@ -410,7 +410,8 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
|
|||
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
||||
|
||||
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT |
|
||||
MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
||||
MMC_MODE_HS_52MHz | MMC_MODE_HS |
|
||||
MMC_MODE_HC;
|
||||
|
||||
/*
|
||||
* SSPCLK = 480 * 18 / 29 / 1 = 297.731 MHz
|
||||
|
|
|
|||
|
|
@ -980,6 +980,8 @@ static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
|
|||
if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
|
||||
debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
|
||||
memcpy(edev->enetaddr, ethaddr, 6);
|
||||
if (!getenv("ethaddr"))
|
||||
eth_setenv_enetaddr("ethaddr", ethaddr);
|
||||
}
|
||||
return ret;
|
||||
err3:
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
|
|||
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
|
||||
COBJS-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
|
||||
COBJS-$(CONFIG_FSL_LPUART) += serial_lpuart.o
|
||||
COBJS-$(CONFIG_MXS_AUART) += mxs_auart.o
|
||||
|
||||
ifndef CONFIG_SPL_BUILD
|
||||
COBJS-$(CONFIG_USB_TTY) += usbtty.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,151 @@
|
|||
/*
|
||||
* Freescale i.MX23/i.MX28 AUART driver
|
||||
*
|
||||
* Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com>
|
||||
*
|
||||
* Based on the MXC serial driver:
|
||||
*
|
||||
* (c) 2007 Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* Further based on the Linux mxs-auart.c driver:
|
||||
*
|
||||
* Freescale STMP37XX/STMP38X Application UART drkiver
|
||||
* Copyright 2008-2010 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <asm/io.h>
|
||||
#include <serial.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/arch/regs-base.h>
|
||||
#include <asm/arch/regs-uartapp.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#ifndef CONFIG_MXS_AUART_BASE
|
||||
#error "CONFIG_MXS_AUART_BASE must be set to the base UART to use"
|
||||
#endif
|
||||
|
||||
/* AUART clock always supplied by XTAL and always 24MHz */
|
||||
#define MXS_AUART_CLK 24000000
|
||||
|
||||
static struct mxs_uartapp_regs *get_uartapp_registers(void)
|
||||
{
|
||||
return (struct mxs_uartapp_regs *)CONFIG_MXS_AUART_BASE;
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets the baud rate and settings.
|
||||
* The settings are: 8 data bits, no parit and 1 stop bit.
|
||||
*/
|
||||
void mxs_auart_setbrg(void)
|
||||
{
|
||||
u32 div;
|
||||
u32 linectrl = 0;
|
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers();
|
||||
|
||||
if (!gd->baudrate)
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
|
||||
/*
|
||||
* From i.MX28 datasheet:
|
||||
* div is calculated by calculating UARTCLK*32/baudrate, rounded to int
|
||||
* div must be between 0xEC and 0x003FFFC0 inclusive
|
||||
* Lowest 6 bits of div goes in BAUD_DIVFRAC part of LINECTRL register
|
||||
* Next 16 bits goes in BAUD_DIVINT part of LINECTRL register
|
||||
*/
|
||||
div = (MXS_AUART_CLK * 32) / gd->baudrate;
|
||||
if (div < 0xEC || div > 0x003FFFC0)
|
||||
return;
|
||||
|
||||
linectrl |= ((div & UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK) <<
|
||||
UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET) &
|
||||
UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK;
|
||||
linectrl |= ((div >> UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET) <<
|
||||
UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET) &
|
||||
UARTAPP_LINECTRL_BAUD_DIVINT_MASK;
|
||||
|
||||
/* Word length: 8 bits */
|
||||
linectrl |= UARTAPP_LINECTRL_WLEN_8BITS;
|
||||
|
||||
/* Enable FIFOs. */
|
||||
linectrl |= UARTAPP_LINECTRL_FEN_MASK;
|
||||
|
||||
/* Write above settings, no parity, 1 stop bit */
|
||||
writel(linectrl, ®s->hw_uartapp_linectrl);
|
||||
}
|
||||
|
||||
int mxs_auart_init(void)
|
||||
{
|
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers();
|
||||
/* Reset everything */
|
||||
mxs_reset_block(®s->hw_uartapp_ctrl0_reg);
|
||||
/* Disable interrupts */
|
||||
writel(0, ®s->hw_uartapp_intr);
|
||||
/* Set baud rate and settings */
|
||||
serial_setbrg();
|
||||
/* Disable RTS and CTS, ignore LINECTRL2 register */
|
||||
writel(UARTAPP_CTRL2_RTSEN_MASK |
|
||||
UARTAPP_CTRL2_CTSEN_MASK |
|
||||
UARTAPP_CTRL2_USE_LCR2_MASK,
|
||||
®s->hw_uartapp_ctrl2_clr);
|
||||
/* Enable receiver, transmitter and UART */
|
||||
writel(UARTAPP_CTRL2_RXE_MASK |
|
||||
UARTAPP_CTRL2_TXE_MASK |
|
||||
UARTAPP_CTRL2_UARTEN_MASK,
|
||||
®s->hw_uartapp_ctrl2_set);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mxs_auart_putc(const char c)
|
||||
{
|
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers();
|
||||
/* Wait in loop while the transmit FIFO is full */
|
||||
while (readl(®s->hw_uartapp_stat) & UARTAPP_STAT_TXFF_MASK)
|
||||
;
|
||||
|
||||
writel(c, ®s->hw_uartapp_data);
|
||||
|
||||
if (c == '\n')
|
||||
mxs_auart_putc('\r');
|
||||
}
|
||||
|
||||
int mxs_auart_tstc(void)
|
||||
{
|
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers();
|
||||
/* Checks if receive FIFO is empty */
|
||||
return !(readl(®s->hw_uartapp_stat) & UARTAPP_STAT_RXFE_MASK);
|
||||
}
|
||||
|
||||
int mxs_auart_getc(void)
|
||||
{
|
||||
struct mxs_uartapp_regs *regs = get_uartapp_registers();
|
||||
/* Wait until a character is available to read */
|
||||
while (!mxs_auart_tstc())
|
||||
;
|
||||
/* Read the character from the data register */
|
||||
return readl(®s->hw_uartapp_data) & 0xFF;
|
||||
}
|
||||
|
||||
static struct serial_device mxs_auart_drv = {
|
||||
.name = "mxs_auart_serial",
|
||||
.start = mxs_auart_init,
|
||||
.stop = NULL,
|
||||
.setbrg = mxs_auart_setbrg,
|
||||
.putc = mxs_auart_putc,
|
||||
.puts = default_serial_puts,
|
||||
.getc = mxs_auart_getc,
|
||||
.tstc = mxs_auart_tstc,
|
||||
};
|
||||
|
||||
void mxs_auart_initialize(void)
|
||||
{
|
||||
serial_register(&mxs_auart_drv);
|
||||
}
|
||||
|
||||
__weak struct serial_device *default_serial_console(void)
|
||||
{
|
||||
return &mxs_auart_drv;
|
||||
}
|
||||
|
|
@ -160,6 +160,7 @@ serial_initfunc(s3c44b0_serial_initialize);
|
|||
serial_initfunc(sa1100_serial_initialize);
|
||||
serial_initfunc(sh_serial_initialize);
|
||||
serial_initfunc(arm_dcc_initialize);
|
||||
serial_initfunc(mxs_auart_initialize);
|
||||
|
||||
/**
|
||||
* serial_register() - Register serial driver with serial driver core
|
||||
|
|
@ -253,6 +254,7 @@ void serial_initialize(void)
|
|||
sa1100_serial_initialize();
|
||||
sh_serial_initialize();
|
||||
arm_dcc_initialize();
|
||||
mxs_auart_initialize();
|
||||
|
||||
serial_assign(default_serial_console()->name);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -119,11 +119,16 @@
|
|||
/* GPIO */
|
||||
#define CONFIG_MXS_GPIO
|
||||
|
||||
/* DUART Serial Driver */
|
||||
/*
|
||||
* DUART Serial Driver.
|
||||
* Conflicts with AUART driver which can be set by board.
|
||||
*/
|
||||
#ifndef CONFIG_MXS_AUART
|
||||
#define CONFIG_PL011_SERIAL
|
||||
#define CONFIG_PL011_CLOCK 24000000
|
||||
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
|
||||
#define CONFIG_CONS_INDEX 0
|
||||
#endif
|
||||
/* Default baudrate can be overriden by board! */
|
||||
#ifndef CONFIG_BAUDRATE
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
|
|
|||
|
|
@ -212,6 +212,7 @@ struct lmb;
|
|||
#define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */
|
||||
#define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */
|
||||
#define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */
|
||||
#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */
|
||||
|
||||
/*
|
||||
* Compression Types
|
||||
|
|
|
|||
|
|
@ -70,31 +70,32 @@ EXT_OBJ_FILES-y += lib/md5.o
|
|||
EXT_OBJ_FILES-y += lib/sha1.o
|
||||
|
||||
# Source files located in the tools directory
|
||||
OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
|
||||
OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
|
||||
NOPED_OBJ_FILES-y += default_image.o
|
||||
NOPED_OBJ_FILES-y += proftool.o
|
||||
OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
|
||||
NOPED_OBJ_FILES-y += fit_image.o
|
||||
OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
|
||||
OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
|
||||
OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
|
||||
NOPED_OBJ_FILES-y += aisimage.o
|
||||
NOPED_OBJ_FILES-y += kwbimage.o
|
||||
NOPED_OBJ_FILES-y += pblimage.o
|
||||
NOPED_OBJ_FILES-y += imximage.o
|
||||
NOPED_OBJ_FILES-y += default_image.o
|
||||
NOPED_OBJ_FILES-y += fit_image.o
|
||||
NOPED_OBJ_FILES-y += image-host.o
|
||||
NOPED_OBJ_FILES-y += omapimage.o
|
||||
NOPED_OBJ_FILES-y += imximage.o
|
||||
NOPED_OBJ_FILES-y += kwbimage.o
|
||||
NOPED_OBJ_FILES-y += mkenvimage.o
|
||||
NOPED_OBJ_FILES-y += mkimage.o
|
||||
OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
|
||||
NOPED_OBJ_FILES-y += mxsimage.o
|
||||
NOPED_OBJ_FILES-y += omapimage.o
|
||||
NOPED_OBJ_FILES-y += os_support.o
|
||||
NOPED_OBJ_FILES-y += pblimage.o
|
||||
NOPED_OBJ_FILES-y += proftool.o
|
||||
NOPED_OBJ_FILES-y += ublimage.o
|
||||
OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
|
||||
OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
|
||||
OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
|
||||
OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
|
||||
OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
|
||||
OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
|
||||
OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
|
||||
OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
|
||||
NOPED_OBJ_FILES-y += os_support.o
|
||||
OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
|
||||
NOPED_OBJ_FILES-y += ublimage.o
|
||||
OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
|
||||
OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
|
||||
OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
|
||||
OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
|
||||
|
||||
# Don't build by default
|
||||
#ifeq ($(ARCH),ppc)
|
||||
|
|
@ -203,20 +204,21 @@ $(obj)mkenvimage$(SFX): $(obj)crc32.o $(obj)mkenvimage.o \
|
|||
$(HOSTSTRIP) $@
|
||||
|
||||
$(obj)mkimage$(SFX): $(obj)aisimage.o \
|
||||
$(FIT_SIG_OBJS) \
|
||||
$(obj)crc32.o \
|
||||
$(obj)default_image.o \
|
||||
$(obj)fit_image.o \
|
||||
$(obj)image-fit.o \
|
||||
$(obj)image.o \
|
||||
$(obj)image-host.o \
|
||||
$(FIT_SIG_OBJS) \
|
||||
$(obj)image.o \
|
||||
$(obj)imximage.o \
|
||||
$(obj)kwbimage.o \
|
||||
$(obj)pblimage.o \
|
||||
$(obj)md5.o \
|
||||
$(obj)mkimage.o \
|
||||
$(obj)os_support.o \
|
||||
$(obj)mxsimage.o \
|
||||
$(obj)omapimage.o \
|
||||
$(obj)os_support.o \
|
||||
$(obj)pblimage.o \
|
||||
$(obj)sha1.o \
|
||||
$(obj)ublimage.o \
|
||||
$(LIBFDT_OBJS) \
|
||||
|
|
|
|||
180
tools/imximage.c
180
tools/imximage.c
|
|
@ -13,6 +13,8 @@
|
|||
#include <image.h>
|
||||
#include "imximage.h"
|
||||
|
||||
#define UNDEFINED 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Supported commands for configuration file
|
||||
*/
|
||||
|
|
@ -20,6 +22,7 @@ static table_entry_t imximage_cmds[] = {
|
|||
{CMD_BOOT_FROM, "BOOT_FROM", "boot command", },
|
||||
{CMD_BOOT_OFFSET, "BOOT_OFFSET", "Boot offset", },
|
||||
{CMD_DATA, "DATA", "Reg Write Data", },
|
||||
{CMD_CSF, "CSF", "Command Sequence File", },
|
||||
{CMD_IMAGE_VERSION, "IMAGE_VERSION", "image version", },
|
||||
{-1, "", "", },
|
||||
};
|
||||
|
|
@ -28,7 +31,7 @@ static table_entry_t imximage_cmds[] = {
|
|||
* Supported Boot options for configuration file
|
||||
* this is needed to set the correct flash offset
|
||||
*/
|
||||
static table_entry_t imximage_bootops[] = {
|
||||
static table_entry_t imximage_boot_offset[] = {
|
||||
{FLASH_OFFSET_ONENAND, "onenand", "OneNAND Flash",},
|
||||
{FLASH_OFFSET_NAND, "nand", "NAND Flash", },
|
||||
{FLASH_OFFSET_NOR, "nor", "NOR Flash", },
|
||||
|
|
@ -38,6 +41,20 @@ static table_entry_t imximage_bootops[] = {
|
|||
{-1, "", "Invalid", },
|
||||
};
|
||||
|
||||
/*
|
||||
* Supported Boot options for configuration file
|
||||
* this is needed to determine the initial load size
|
||||
*/
|
||||
static table_entry_t imximage_boot_loadsize[] = {
|
||||
{FLASH_LOADSIZE_ONENAND, "onenand", "OneNAND Flash",},
|
||||
{FLASH_LOADSIZE_NAND, "nand", "NAND Flash", },
|
||||
{FLASH_LOADSIZE_NOR, "nor", "NOR Flash", },
|
||||
{FLASH_LOADSIZE_SATA, "sata", "SATA Disk", },
|
||||
{FLASH_LOADSIZE_SD, "sd", "SD Card", },
|
||||
{FLASH_LOADSIZE_SPI, "spi", "SPI Flash", },
|
||||
{-1, "", "Invalid", },
|
||||
};
|
||||
|
||||
/*
|
||||
* IMXIMAGE version definition for i.MX chips
|
||||
*/
|
||||
|
|
@ -49,12 +66,22 @@ static table_entry_t imximage_versions[] = {
|
|||
|
||||
static struct imx_header imximage_header;
|
||||
static uint32_t imximage_version;
|
||||
/*
|
||||
* Image Vector Table Offset
|
||||
* Initialized to a wrong not 4-bytes aligned address to
|
||||
* check if it is was set by the cfg file.
|
||||
*/
|
||||
static uint32_t imximage_ivt_offset = UNDEFINED;
|
||||
static uint32_t imximage_csf_size = UNDEFINED;
|
||||
/* Initial Load Region Size */
|
||||
static uint32_t imximage_init_loadsize;
|
||||
|
||||
static set_dcd_val_t set_dcd_val;
|
||||
static set_dcd_rst_t set_dcd_rst;
|
||||
static set_imx_hdr_t set_imx_hdr;
|
||||
static uint32_t max_dcd_entries;
|
||||
static uint32_t *header_size_ptr;
|
||||
static uint32_t *csf_ptr;
|
||||
|
||||
static uint32_t get_cfg_value(char *token, char *name, int linenr)
|
||||
{
|
||||
|
|
@ -190,7 +217,8 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, uint32_t dcd_len,
|
|||
/* Set magic number */
|
||||
fhdr_v1->app_code_barker = APP_CODE_BARKER;
|
||||
|
||||
hdr_base = entry_point - sizeof(struct imx_header);
|
||||
/* TODO: check i.MX image V1 handling, for now use 'old' style */
|
||||
hdr_base = entry_point - 4096;
|
||||
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
|
||||
fhdr_v1->app_code_jump_vector = entry_point;
|
||||
|
||||
|
|
@ -217,16 +245,18 @@ static void set_imx_hdr_v2(struct imx_header *imxhdr, uint32_t dcd_len,
|
|||
|
||||
fhdr_v2->entry = entry_point;
|
||||
fhdr_v2->reserved1 = fhdr_v2->reserved2 = 0;
|
||||
fhdr_v2->self = hdr_base = entry_point - sizeof(struct imx_header);
|
||||
|
||||
hdr_base = entry_point - imximage_init_loadsize +
|
||||
flash_offset;
|
||||
fhdr_v2->self = hdr_base;
|
||||
fhdr_v2->dcd_ptr = hdr_base + offsetof(imx_header_v2_t, dcd_table);
|
||||
fhdr_v2->boot_data_ptr = hdr_base
|
||||
+ offsetof(imx_header_v2_t, boot_data);
|
||||
hdr_v2->boot_data.start = hdr_base - flash_offset;
|
||||
hdr_v2->boot_data.start = entry_point - imximage_init_loadsize;
|
||||
|
||||
/* Security feature are not supported */
|
||||
fhdr_v2->csf = 0;
|
||||
|
||||
header_size_ptr = &hdr_v2->boot_data.size;
|
||||
csf_ptr = &fhdr_v2->csf;
|
||||
}
|
||||
|
||||
static void set_hdr_func(struct imx_header *imxhdr)
|
||||
|
|
@ -303,6 +333,13 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
|
|||
genimg_print_size(hdr_v2->boot_data.size);
|
||||
printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
|
||||
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
|
||||
if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) &&
|
||||
(imximage_csf_size != UNDEFINED)) {
|
||||
printf("HAB Blocks: %08x %08x %08x\n",
|
||||
(uint32_t)fhdr_v2->self, 0,
|
||||
hdr_v2->boot_data.size - imximage_ivt_offset -
|
||||
imximage_csf_size);
|
||||
}
|
||||
}
|
||||
|
||||
static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
|
||||
|
|
@ -324,18 +361,36 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
|
|||
set_hdr_func(imxhdr);
|
||||
break;
|
||||
case CMD_BOOT_FROM:
|
||||
imxhdr->flash_offset = get_table_entry_id(imximage_bootops,
|
||||
imximage_ivt_offset = get_table_entry_id(imximage_boot_offset,
|
||||
"imximage boot option", token);
|
||||
if (imxhdr->flash_offset == -1) {
|
||||
if (imximage_ivt_offset == -1) {
|
||||
fprintf(stderr, "Error: %s[%d] -Invalid boot device"
|
||||
"(%s)\n", name, lineno, token);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
imximage_init_loadsize =
|
||||
get_table_entry_id(imximage_boot_loadsize,
|
||||
"imximage boot option", token);
|
||||
|
||||
if (imximage_init_loadsize == -1) {
|
||||
fprintf(stderr,
|
||||
"Error: %s[%d] -Invalid boot device(%s)\n",
|
||||
name, lineno, token);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
/*
|
||||
* The SOC loads from the storage starting at address 0
|
||||
* then ensures that the load size contains the offset
|
||||
*/
|
||||
if (imximage_init_loadsize < imximage_ivt_offset)
|
||||
imximage_init_loadsize = imximage_ivt_offset;
|
||||
if (unlikely(cmd_ver_first != 1))
|
||||
cmd_ver_first = 0;
|
||||
break;
|
||||
case CMD_BOOT_OFFSET:
|
||||
imxhdr->flash_offset = get_cfg_value(token, name, lineno);
|
||||
imximage_ivt_offset = get_cfg_value(token, name, lineno);
|
||||
if (unlikely(cmd_ver_first != 1))
|
||||
cmd_ver_first = 0;
|
||||
break;
|
||||
|
|
@ -345,6 +400,17 @@ static void parse_cfg_cmd(struct imx_header *imxhdr, int32_t cmd, char *token,
|
|||
if (unlikely(cmd_ver_first != 1))
|
||||
cmd_ver_first = 0;
|
||||
break;
|
||||
case CMD_CSF:
|
||||
if (imximage_version != 2) {
|
||||
fprintf(stderr,
|
||||
"Error: %s[%d] - CSF only supported for VERSION 2(%s)\n",
|
||||
name, lineno, token);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
imximage_csf_size = get_cfg_value(token, name, lineno);
|
||||
if (unlikely(cmd_ver_first != 1))
|
||||
cmd_ver_first = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -405,7 +471,8 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
|
|||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
/* Very simple parsing, line starting with # are comments
|
||||
/*
|
||||
* Very simple parsing, line starting with # are comments
|
||||
* and are dropped
|
||||
*/
|
||||
while ((getline(&line, &len, fd)) > 0) {
|
||||
|
|
@ -436,7 +503,7 @@ static uint32_t parse_cfg_file(struct imx_header *imxhdr, char *name)
|
|||
fclose(fd);
|
||||
|
||||
/* Exit if there is no BOOT_FROM field specifying the flash_offset */
|
||||
if (imxhdr->flash_offset == FLASH_OFFSET_UNDEFINED) {
|
||||
if (imximage_ivt_offset == FLASH_OFFSET_UNDEFINED) {
|
||||
fprintf(stderr, "Error: No BOOT_FROM tag in %s\n", name);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
|
@ -494,14 +561,15 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
|
|||
*/
|
||||
imximage_version = IMXIMAGE_V1;
|
||||
/* Be able to detect if the cfg file has no BOOT_FROM tag */
|
||||
imxhdr->flash_offset = FLASH_OFFSET_UNDEFINED;
|
||||
imximage_ivt_offset = FLASH_OFFSET_UNDEFINED;
|
||||
imximage_csf_size = 0;
|
||||
set_hdr_func(imxhdr);
|
||||
|
||||
/* Parse dcd configuration file */
|
||||
dcd_len = parse_cfg_file(imxhdr, params->imagename);
|
||||
|
||||
/* Set the imx header */
|
||||
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imxhdr->flash_offset);
|
||||
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
|
||||
|
||||
/*
|
||||
* ROM bug alert
|
||||
|
|
@ -512,7 +580,13 @@ static void imximage_set_header(void *ptr, struct stat *sbuf, int ifd,
|
|||
*
|
||||
* The remaining fraction of a block bytes would not be loaded!
|
||||
*/
|
||||
*header_size_ptr = ROUND(sbuf->st_size + imxhdr->flash_offset, 4096);
|
||||
*header_size_ptr = ROUND(sbuf->st_size, 4096);
|
||||
|
||||
if (csf_ptr && imximage_csf_size) {
|
||||
*csf_ptr = params->ep - imximage_init_loadsize +
|
||||
*header_size_ptr;
|
||||
*header_size_ptr += imximage_csf_size;
|
||||
}
|
||||
}
|
||||
|
||||
int imximage_check_params(struct mkimage_params *params)
|
||||
|
|
@ -537,18 +611,92 @@ int imximage_check_params(struct mkimage_params *params)
|
|||
(params->xflag) || !(strlen(params->imagename));
|
||||
}
|
||||
|
||||
static int imximage_generate(struct mkimage_params *params,
|
||||
struct image_type_params *tparams)
|
||||
{
|
||||
struct imx_header *imxhdr;
|
||||
size_t alloc_len;
|
||||
struct stat sbuf;
|
||||
char *datafile = params->datafile;
|
||||
uint32_t pad_len;
|
||||
|
||||
memset(&imximage_header, 0, sizeof(imximage_header));
|
||||
|
||||
/*
|
||||
* In order to not change the old imx cfg file
|
||||
* by adding VERSION command into it, here need
|
||||
* set up function ptr group to V1 by default.
|
||||
*/
|
||||
imximage_version = IMXIMAGE_V1;
|
||||
/* Be able to detect if the cfg file has no BOOT_FROM tag */
|
||||
imximage_ivt_offset = FLASH_OFFSET_UNDEFINED;
|
||||
imximage_csf_size = 0;
|
||||
set_hdr_func(imxhdr);
|
||||
|
||||
/* Parse dcd configuration file */
|
||||
parse_cfg_file(&imximage_header, params->imagename);
|
||||
|
||||
/* TODO: check i.MX image V1 handling, for now use 'old' style */
|
||||
if (imximage_version == IMXIMAGE_V1) {
|
||||
alloc_len = 4096;
|
||||
} else {
|
||||
if (imximage_init_loadsize < imximage_ivt_offset +
|
||||
sizeof(imx_header_v2_t))
|
||||
imximage_init_loadsize = imximage_ivt_offset +
|
||||
sizeof(imx_header_v2_t);
|
||||
alloc_len = imximage_init_loadsize - imximage_ivt_offset;
|
||||
}
|
||||
|
||||
if (alloc_len < sizeof(struct imx_header)) {
|
||||
fprintf(stderr, "%s: header error\n",
|
||||
params->cmdname);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
imxhdr = malloc(alloc_len);
|
||||
|
||||
if (!imxhdr) {
|
||||
fprintf(stderr, "%s: malloc return failure: %s\n",
|
||||
params->cmdname, strerror(errno));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
memset(imxhdr, 0, alloc_len);
|
||||
|
||||
tparams->header_size = alloc_len;
|
||||
tparams->hdr = imxhdr;
|
||||
|
||||
/* determine data image file length */
|
||||
|
||||
if (stat(datafile, &sbuf) < 0) {
|
||||
fprintf(stderr, "%s: Can't stat %s: %s\n",
|
||||
params->cmdname, datafile, strerror(errno));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size;
|
||||
|
||||
/* TODO: check i.MX image V1 handling, for now use 'old' style */
|
||||
if (imximage_version == IMXIMAGE_V1)
|
||||
return 0;
|
||||
else
|
||||
return pad_len;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* imximage parameters
|
||||
*/
|
||||
static struct image_type_params imximage_params = {
|
||||
.name = "Freescale i.MX Boot Image support",
|
||||
.header_size = sizeof(struct imx_header),
|
||||
.hdr = (void *)&imximage_header,
|
||||
.header_size = 0,
|
||||
.hdr = NULL,
|
||||
.check_image_type = imximage_check_image_types,
|
||||
.verify_header = imximage_verify_header,
|
||||
.print_header = imximage_print_header,
|
||||
.set_header = imximage_set_header,
|
||||
.check_params = imximage_check_params,
|
||||
.vrec_header = imximage_generate,
|
||||
};
|
||||
|
||||
void init_imx_image_type(void)
|
||||
|
|
|
|||
|
|
@ -13,14 +13,14 @@
|
|||
#define APP_CODE_BARKER 0xB1
|
||||
#define DCD_BARKER 0xB17219E9
|
||||
|
||||
#define HEADER_OFFSET 0x400
|
||||
|
||||
/*
|
||||
* NOTE: This file must be kept in sync with arch/arm/include/asm/\
|
||||
* imx-common/imximage.cfg because tools/imximage.c can not
|
||||
* cross-include headers from arch/arm/ and vice-versa.
|
||||
*/
|
||||
#define CMD_DATA_STR "DATA"
|
||||
|
||||
/* Initial Vector Table Offset */
|
||||
#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
|
||||
#define FLASH_OFFSET_STANDARD 0x400
|
||||
#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
|
||||
|
|
@ -30,6 +30,16 @@
|
|||
#define FLASH_OFFSET_NOR 0x1000
|
||||
#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
|
||||
|
||||
/* Initial Load Region Size */
|
||||
#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
|
||||
#define FLASH_LOADSIZE_STANDARD 0x1000
|
||||
#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
|
||||
#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
|
||||
#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
|
||||
#define FLASH_LOADSIZE_ONENAND 0x400
|
||||
#define FLASH_LOADSIZE_NOR 0x0 /* entire image */
|
||||
#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
|
||||
|
||||
#define IVT_HEADER_TAG 0xD1
|
||||
#define IVT_VERSION 0x40
|
||||
#define DCD_HEADER_TAG 0xD2
|
||||
|
|
@ -42,7 +52,8 @@ enum imximage_cmd {
|
|||
CMD_IMAGE_VERSION,
|
||||
CMD_BOOT_FROM,
|
||||
CMD_BOOT_OFFSET,
|
||||
CMD_DATA
|
||||
CMD_DATA,
|
||||
CMD_CSF,
|
||||
};
|
||||
|
||||
enum imximage_fld_types {
|
||||
|
|
@ -147,8 +158,7 @@ struct imx_header {
|
|||
imx_header_v1_t hdr_v1;
|
||||
imx_header_v2_t hdr_v2;
|
||||
} header;
|
||||
uint32_t flash_offset;
|
||||
} __attribute__((aligned(4096)));
|
||||
};
|
||||
|
||||
typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
|
||||
char *name, int lineno,
|
||||
|
|
|
|||
|
|
@ -137,6 +137,7 @@ main (int argc, char **argv)
|
|||
char *ptr;
|
||||
int retval = 0;
|
||||
struct image_type_params *tparams = NULL;
|
||||
int pad_len = 0;
|
||||
|
||||
/* Init Freescale PBL Boot image generation/list support */
|
||||
init_pbl_image_type();
|
||||
|
|
@ -144,6 +145,8 @@ main (int argc, char **argv)
|
|||
init_kwb_image_type ();
|
||||
/* Init Freescale imx Boot image generation/list support */
|
||||
init_imx_image_type ();
|
||||
/* Init Freescale mxs Boot image generation/list support */
|
||||
init_mxs_image_type();
|
||||
/* Init FIT image generation/list support */
|
||||
init_fit_image_type ();
|
||||
/* Init TI OMAP Boot image generation/list support */
|
||||
|
|
@ -391,7 +394,7 @@ NXTARG: ;
|
|||
* allocate memory for the header itself.
|
||||
*/
|
||||
if (tparams->vrec_header)
|
||||
tparams->vrec_header(¶ms, tparams);
|
||||
pad_len = tparams->vrec_header(¶ms, tparams);
|
||||
else
|
||||
memset(tparams->hdr, 0, tparams->header_size);
|
||||
|
||||
|
|
@ -463,7 +466,7 @@ NXTARG: ;
|
|||
/* PBL has special Image format, implements its' own */
|
||||
pbl_load_uboot(ifd, ¶ms);
|
||||
} else {
|
||||
copy_file (ifd, params.datafile, 0);
|
||||
copy_file(ifd, params.datafile, pad_len);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -537,10 +540,19 @@ copy_file (int ifd, const char *datafile, int pad)
|
|||
unsigned char *ptr;
|
||||
int tail;
|
||||
int zero = 0;
|
||||
uint8_t zeros[4096];
|
||||
int offset = 0;
|
||||
int size;
|
||||
struct image_type_params *tparams = mkimage_get_type (params.type);
|
||||
|
||||
if (pad >= sizeof(zeros)) {
|
||||
fprintf(stderr, "%s: Can't pad to %d\n",
|
||||
params.cmdname, pad);
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
memset(zeros, 0, sizeof(zeros));
|
||||
|
||||
if (params.vflag) {
|
||||
fprintf (stderr, "Adding Image %s\n", datafile);
|
||||
}
|
||||
|
|
@ -598,7 +610,8 @@ copy_file (int ifd, const char *datafile, int pad)
|
|||
exit (EXIT_FAILURE);
|
||||
}
|
||||
|
||||
if (pad && ((tail = size % 4) != 0)) {
|
||||
tail = size % 4;
|
||||
if ((pad == 1) && (tail != 0)) {
|
||||
|
||||
if (write(ifd, (char *)&zero, 4-tail) != 4-tail) {
|
||||
fprintf (stderr, "%s: Write error on %s: %s\n",
|
||||
|
|
@ -606,6 +619,13 @@ copy_file (int ifd, const char *datafile, int pad)
|
|||
strerror(errno));
|
||||
exit (EXIT_FAILURE);
|
||||
}
|
||||
} else if (pad > 1) {
|
||||
if (write(ifd, (char *)&zeros, pad) != pad) {
|
||||
fprintf(stderr, "%s: Write error on %s: %s\n",
|
||||
params.cmdname, params.imagefile,
|
||||
strerror(errno));
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
}
|
||||
|
||||
(void) munmap((void *)ptr, sbuf.st_size);
|
||||
|
|
|
|||
|
|
@ -132,7 +132,10 @@ struct image_type_params {
|
|||
/*
|
||||
* This callback function will be executed for variable size record
|
||||
* It is expected to build this header in memory and return its length
|
||||
* and a pointer to it
|
||||
* and a pointer to it by using image_type_params.header_size and
|
||||
* image_type_params.hdr. The return value shall indicate if an
|
||||
* additional padding should be used when copying the data image
|
||||
* by returning the padding length.
|
||||
*/
|
||||
int (*vrec_header) (struct mkimage_params *,
|
||||
struct image_type_params *);
|
||||
|
|
@ -158,6 +161,7 @@ void init_pbl_image_type(void);
|
|||
void init_ais_image_type(void);
|
||||
void init_kwb_image_type (void);
|
||||
void init_imx_image_type (void);
|
||||
void init_mxs_image_type(void);
|
||||
void init_default_image_type (void);
|
||||
void init_fit_image_type (void);
|
||||
void init_ubl_image_type(void);
|
||||
|
|
|
|||
|
|
@ -28,14 +28,14 @@
|
|||
*
|
||||
* TWEAK this if you have different kind of NAND chip.
|
||||
*/
|
||||
uint32_t nand_writesize = 2048;
|
||||
uint32_t nand_oobsize = 64;
|
||||
uint32_t nand_erasesize = 128 * 1024;
|
||||
static uint32_t nand_writesize = 2048;
|
||||
static uint32_t nand_oobsize = 64;
|
||||
static uint32_t nand_erasesize = 128 * 1024;
|
||||
|
||||
/*
|
||||
* Sector on which the SigmaTel boot partition (0x53) starts.
|
||||
*/
|
||||
uint32_t sd_sector = 2048;
|
||||
static uint32_t sd_sector = 2048;
|
||||
|
||||
/*
|
||||
* Each of the U-Boot bootstreams is at maximum 1MB big.
|
||||
|
|
@ -434,7 +434,7 @@ static int mx28_nand_write_firmware(struct mx28_nand_fcb *fcb, int infd,
|
|||
return 0;
|
||||
}
|
||||
|
||||
void usage(void)
|
||||
static void usage(void)
|
||||
{
|
||||
printf(
|
||||
"Usage: mxsboot [ops] <type> <infile> <outfile>\n"
|
||||
|
|
@ -575,7 +575,7 @@ err0:
|
|||
return ret;
|
||||
}
|
||||
|
||||
int parse_ops(int argc, char **argv)
|
||||
static int parse_ops(int argc, char **argv)
|
||||
{
|
||||
int i;
|
||||
int tmp;
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,230 @@
|
|||
/*
|
||||
* Freescale i.MX28 SB image generator
|
||||
*
|
||||
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __MXSSB_H__
|
||||
#define __MXSSB_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <arpa/inet.h>
|
||||
|
||||
#define SB_BLOCK_SIZE 16
|
||||
|
||||
#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
struct sb_boot_image_version {
|
||||
uint16_t major;
|
||||
uint16_t pad0;
|
||||
uint16_t minor;
|
||||
uint16_t pad1;
|
||||
uint16_t revision;
|
||||
uint16_t pad2;
|
||||
};
|
||||
|
||||
struct sb_boot_image_header {
|
||||
union {
|
||||
/* SHA1 of the header. */
|
||||
uint8_t digest[20];
|
||||
struct {
|
||||
/* CBC-MAC initialization vector. */
|
||||
uint8_t iv[16];
|
||||
uint8_t extra[4];
|
||||
};
|
||||
};
|
||||
/* 'STMP' */
|
||||
uint8_t signature1[4];
|
||||
/* Major version of the image format. */
|
||||
uint8_t major_version;
|
||||
/* Minor version of the image format. */
|
||||
uint8_t minor_version;
|
||||
/* Flags associated with the image. */
|
||||
uint16_t flags;
|
||||
/* Size of the image in 16b blocks. */
|
||||
uint32_t image_blocks;
|
||||
/* Offset of the first tag in 16b blocks. */
|
||||
uint32_t first_boot_tag_block;
|
||||
/* ID of the section to boot from. */
|
||||
uint32_t first_boot_section_id;
|
||||
/* Amount of crypto keys. */
|
||||
uint16_t key_count;
|
||||
/* Offset to the key dictionary in 16b blocks. */
|
||||
uint16_t key_dictionary_block;
|
||||
/* Size of this header in 16b blocks. */
|
||||
uint16_t header_blocks;
|
||||
/* Amount of section headers. */
|
||||
uint16_t section_count;
|
||||
/* Section header size in 16b blocks. */
|
||||
uint16_t section_header_size;
|
||||
/* Padding to align timestamp to uint64_t. */
|
||||
uint8_t padding0[2];
|
||||
/* 'sgtl' (since v1.1) */
|
||||
uint8_t signature2[4];
|
||||
/* Image generation date, in microseconds since 1.1.2000 . */
|
||||
uint64_t timestamp_us;
|
||||
/* Product version. */
|
||||
struct sb_boot_image_version
|
||||
product_version;
|
||||
/* Component version. */
|
||||
struct sb_boot_image_version
|
||||
component_version;
|
||||
/* Drive tag for the system drive. (since v1.1) */
|
||||
uint16_t drive_tag;
|
||||
/* Padding. */
|
||||
uint8_t padding1[6];
|
||||
};
|
||||
|
||||
#define SB_VERSION_MAJOR 1
|
||||
#define SB_VERSION_MINOR 1
|
||||
|
||||
/* Enable to HTLLC verbose boot report. */
|
||||
#define SB_IMAGE_FLAG_VERBOSE (1 << 0)
|
||||
|
||||
struct sb_key_dictionary_key {
|
||||
/* The CBC-MAC of image and sections header. */
|
||||
uint8_t cbc_mac[SB_BLOCK_SIZE];
|
||||
/* The AES key encrypted by image key (zero). */
|
||||
uint8_t key[SB_BLOCK_SIZE];
|
||||
};
|
||||
|
||||
struct sb_ivt_header {
|
||||
uint32_t header;
|
||||
uint32_t entry;
|
||||
uint32_t reserved1;
|
||||
uint32_t dcd;
|
||||
uint32_t boot_data;
|
||||
uint32_t self;
|
||||
uint32_t csf;
|
||||
uint32_t reserved2;
|
||||
};
|
||||
|
||||
#define SB_HAB_IVT_TAG 0xd1UL
|
||||
#define SB_HAB_DCD_TAG 0xd2UL
|
||||
|
||||
#define SB_HAB_VERSION 0x40UL
|
||||
|
||||
/*
|
||||
* The "size" field in the IVT header is not naturally aligned,
|
||||
* use this macro to fill first 4 bytes of the IVT header without
|
||||
* causing issues on some systems (esp. M68k, PPC, MIPS-BE, ARM-BE).
|
||||
*/
|
||||
static inline uint32_t sb_hab_ivt_header(void)
|
||||
{
|
||||
uint32_t ret = 0;
|
||||
ret |= SB_HAB_IVT_TAG << 24;
|
||||
ret |= sizeof(struct sb_ivt_header) << 16;
|
||||
ret |= SB_HAB_VERSION;
|
||||
return htonl(ret);
|
||||
}
|
||||
|
||||
struct sb_sections_header {
|
||||
/* Section number. */
|
||||
uint32_t section_number;
|
||||
/* Offset of this sections first instruction after "TAG". */
|
||||
uint32_t section_offset;
|
||||
/* Size of the section in 16b blocks. */
|
||||
uint32_t section_size;
|
||||
/* Section flags. */
|
||||
uint32_t section_flags;
|
||||
};
|
||||
|
||||
#define SB_SECTION_FLAG_BOOTABLE (1 << 0)
|
||||
|
||||
struct sb_command {
|
||||
struct {
|
||||
uint8_t checksum;
|
||||
uint8_t tag;
|
||||
uint16_t flags;
|
||||
#define ROM_TAG_CMD_FLAG_ROM_LAST_TAG 0x1
|
||||
#define ROM_LOAD_CMD_FLAG_DCD_LOAD 0x1 /* MX28 only */
|
||||
#define ROM_JUMP_CMD_FLAG_HAB 0x1 /* MX28 only */
|
||||
#define ROM_CALL_CMD_FLAG_HAB 0x1 /* MX28 only */
|
||||
} header;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved[3];
|
||||
} nop;
|
||||
struct {
|
||||
uint32_t section_number;
|
||||
uint32_t section_length;
|
||||
uint32_t section_flags;
|
||||
} tag;
|
||||
struct {
|
||||
uint32_t address;
|
||||
uint32_t count;
|
||||
uint32_t crc32;
|
||||
} load;
|
||||
struct {
|
||||
uint32_t address;
|
||||
uint32_t count;
|
||||
uint32_t pattern;
|
||||
} fill;
|
||||
struct {
|
||||
uint32_t address;
|
||||
uint32_t reserved;
|
||||
/* Passed in register r0 before JUMP */
|
||||
uint32_t argument;
|
||||
} jump;
|
||||
struct {
|
||||
uint32_t address;
|
||||
uint32_t reserved;
|
||||
/* Passed in register r0 before CALL */
|
||||
uint32_t argument;
|
||||
} call;
|
||||
struct {
|
||||
uint32_t reserved1;
|
||||
uint32_t reserved2;
|
||||
uint32_t mode;
|
||||
} mode;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* Most of the mode names are same or at least similar
|
||||
* on i.MX23 and i.MX28, but some of the mode names
|
||||
* differ. The "name" field represents the mode name
|
||||
* on i.MX28 as seen in Table 12-2 of the datasheet.
|
||||
* The "altname" field represents the differently named
|
||||
* fields on i.MX23 as seen in Table 35-3 of the
|
||||
* datasheet.
|
||||
*/
|
||||
static const struct {
|
||||
const char *name;
|
||||
const char *altname;
|
||||
const uint8_t mode;
|
||||
} modetable[] = {
|
||||
{ "USB", NULL, 0x00 },
|
||||
{ "I2C", NULL, 0x01 },
|
||||
{ "SPI2_FLASH", "SPI1_FLASH", 0x02 },
|
||||
{ "SPI3_FLASH", "SPI2_FLASH", 0x03 },
|
||||
{ "NAND_BCH", NULL, 0x04 },
|
||||
{ "JTAG", NULL, 0x06 },
|
||||
{ "SPI3_EEPROM", "SPI2_EEPROM", 0x08 },
|
||||
{ "SD_SSP0", NULL, 0x09 },
|
||||
{ "SD_SSP1", NULL, 0x0A }
|
||||
};
|
||||
|
||||
enum sb_tag {
|
||||
ROM_NOP_CMD = 0x00,
|
||||
ROM_TAG_CMD = 0x01,
|
||||
ROM_LOAD_CMD = 0x02,
|
||||
ROM_FILL_CMD = 0x03,
|
||||
ROM_JUMP_CMD = 0x04,
|
||||
ROM_CALL_CMD = 0x05,
|
||||
ROM_MODE_CMD = 0x06
|
||||
};
|
||||
|
||||
struct sb_source_entry {
|
||||
uint8_t tag;
|
||||
uint32_t address;
|
||||
uint32_t flags;
|
||||
char *filename;
|
||||
};
|
||||
|
||||
#endif /* __MXSSB_H__ */
|
||||
Loading…
Reference in New Issue