Bai Ping 7b14cc991b imx8mq: Update the ddrc QoS setting for B1 chip ... Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com>		2019-10-08 16:36:37 +02:00
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ddr4_init.c	ddr: imx8m: Fix ddr4 driver build issue	2019-10-08 16:36:37 +02:00
ddrphy_csr.c	drivers: ddr: introduce DDR driver for i.MX8M	2019-01-01 14:12:18 +01:00
ddrphy_train.c	drivers: ddr: introduce DDR driver for i.MX8M	2019-01-01 14:12:18 +01:00
ddrphy_utils.c	drivers: ddr: introduce DDR driver for i.MX8M	2019-01-01 14:12:18 +01:00
helper.c	ddr: imx8m: fix ddr firmware location when enable SPL OF	2019-10-08 16:36:36 +02:00
Kconfig	ddr: imx8m: hide i.MX8M DDR options from device driver entry	2019-04-25 19:20:04 +02:00
lpddr4_init.c	imx8mq: Update the ddrc QoS setting for B1 chip	2019-10-08 16:36:37 +02:00
Makefile	drivers: ddr: introduce DDR driver for i.MX8M	2019-01-01 14:12:18 +01:00