Bai Ping 7b14cc991b imx8mq: Update the ddrc QoS setting for B1 chip ... Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com>		2019-10-08 16:36:37 +02:00
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altera	dm: ddr: socfpga: fix gen5 ddr driver to not use bss	2019-07-21 12:45:01 +02:00
fsl	ddr, fsl: add DM_I2C support	2019-08-26 21:16:24 +05:30
imx	imx8mq: Update the ddrc QoS setting for B1 chip	2019-10-08 16:36:37 +02:00
marvell	arm: mvebu: Add Marvell's integrated CPUs	2019-04-12 07:04:18 +02:00
microchip	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
Kconfig	drivers: ddr: introduce DDR driver for i.MX8M	2019-01-01 14:12:18 +01:00