mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-27 05:13:44 +09:00
7a4b6964b5
This patch adds SPL support for mtmips platform. The lowlevel architecture is split into SPL and the rest parts are built into a memory loadable u-boot image. Optional SPL_DM and OF_CONTROL are also supported. The increment of size is very small (< 10 KiB) if SPL_DM and OF_CONTROL are not enabled and the memory bootable u-boot (u-boot.img) is generated automatically so there is not need to add a separate config for it. A lzma compressed payload (u-boot-lzma.img) is also generated and it will be combined with u-boot-spl.bin to form the unified ROM bootable binary u-boot-mtmips.bin. A spl loader is added to support uncompress the payload. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
122 lines
2.8 KiB
Plaintext
122 lines
2.8 KiB
Plaintext
menu "MediaTek MIPS platforms"
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depends on ARCH_MTMIPS
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config SYS_MALLOC_F_LEN
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default 0x1000
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config SYS_SOC
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default "mt7628" if SOC_MT7628
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config SYS_DCACHE_SIZE
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default 32768
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config SYS_DCACHE_LINE_SIZE
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default 32
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config SYS_ICACHE_SIZE
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default 65536
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config SYS_ICACHE_LINE_SIZE
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default 32
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config SYS_TEXT_BASE
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default 0x9c000000 if !SPL
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default 0x80200000 if SPL
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config SPL_TEXT_BASE
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default 0x9c000000
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config SPL_PAYLOAD
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default "u-boot-lzma.img" if SPL_LZMA
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config BUILD_TARGET
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default "u-boot-with-spl.bin" if SPL
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choice
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prompt "MediaTek MIPS SoC select"
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config SOC_MT7628
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bool "MT7628"
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select MIPS_L1_CACHE_SHIFT_5
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select MIPS_INIT_STACK_IN_SRAM
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select MIPS_SRAM_INIT
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select SYS_MIPS_CACHE_INIT_RAM_LOAD
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select PINCTRL_MT7628
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select MTK_SERIAL
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select SYSRESET_RESETCTL
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select SPL_SEPARATE_BSS if SPL
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select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
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select SPL_LOADER_SUPPORT if SPL
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select SPL_OF_CONTROL if SPL_DM
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select SPL_SIMPLE_BUS if SPL_DM
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select SPL_DM_SERIAL if SPL_DM
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select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT
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select SPL_SYSRESET if SPL_DM
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select SPL_OF_LIBFDT if SPL_OF_CONTROL
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help
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This supports MediaTek MT7628/MT7688.
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endchoice
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choice
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prompt "Board select"
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config BOARD_GARDENA_SMART_GATEWAY_MT7688
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bool "GARDENA smart Gateway"
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depends on SOC_MT7628
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select BOARD_LATE_INIT
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select SUPPORTS_BOOT_RAM
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help
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GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM
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and 8 MiB of flash (SPI NOR) and additional SPI NAND storage.
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config BOARD_LINKIT_SMART_7688
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bool "LinkIt Smart 7688"
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depends on SOC_MT7628
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select SUPPORTS_BOOT_RAM
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help
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Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM
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and 32 MiB of flash (SPI).
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Between its different peripherals there's an integrated switch with 4
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ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and
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a MT7688 (PCIe).
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endchoice
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choice
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prompt "Boot mode"
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config BOOT_RAM
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bool "RAM boot"
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depends on SUPPORTS_BOOT_RAM
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help
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This builds an image that is linked to a RAM address. It can be used
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for booting from CFE via TFTP using an ELF image, but it can also be
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booted from RAM by other bootloaders using a BIN image.
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config BOOT_ROM
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bool "ROM boot"
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depends on SUPPORTS_BOOT_RAM
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help
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This builds an image that is linked to a ROM address. It can be
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used as main bootloader image which is programmed onto the onboard
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flash storage (SPI NOR).
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endchoice
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config SUPPORTS_BOOT_RAM
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bool
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config SPL_UART2_SPIS_PINMUX
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bool "Use alternative pinmux for UART2 in SPL stage"
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depends on SPL_SERIAL_SUPPORT
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default n
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help
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Select this if the UART2 of your board is connected to GPIO 16/17
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(shared with SPIS) rather than the usual GPIO 20/21.
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source "board/gardena/smart-gateway-mt7688/Kconfig"
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source "board/seeed/linkit-smart-7688/Kconfig"
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endmenu
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