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https://github.com/brain-hackers/u-boot-brain
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mips: mtmips: add SPL support
This patch adds SPL support for mtmips platform. The lowlevel architecture is split into SPL and the rest parts are built into a memory loadable u-boot image. Optional SPL_DM and OF_CONTROL are also supported. The increment of size is very small (< 10 KiB) if SPL_DM and OF_CONTROL are not enabled and the memory bootable u-boot (u-boot.img) is generated automatically so there is not need to add a separate config for it. A lzma compressed payload (u-boot-lzma.img) is also generated and it will be combined with u-boot-spl.bin to form the unified ROM bootable binary u-boot-mtmips.bin. A spl loader is added to support uncompress the payload. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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@ -98,6 +98,7 @@ config ARCH_MTMIPS
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select SUPPORTS_CPU_MIPS32_R2
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select SUPPORTS_LITTLE_ENDIAN
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select SYSRESET
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select SUPPORT_SPL
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config ARCH_JZ47XX
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bool "Support Ingenic JZ47xx"
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38
arch/mips/dts/mt7628-u-boot.dtsi
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38
arch/mips/dts/mt7628-u-boot.dtsi
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@ -0,0 +1,38 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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&palmbus {
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u-boot,dm-pre-reloc;
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};
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&reboot {
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u-boot,dm-pre-reloc;
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};
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&clkctrl {
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u-boot,dm-pre-reloc;
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};
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&rstctrl {
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u-boot,dm-pre-reloc;
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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&uart1 {
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u-boot,dm-pre-reloc;
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};
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&uart2 {
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u-boot,dm-pre-reloc;
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};
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@ -33,7 +33,7 @@
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#clock-cells = <0>;
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};
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palmbus@10000000 {
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palmbus: palmbus@10000000 {
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compatible = "palmbus", "simple-bus";
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reg = <0x10000000 0x200000>;
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ranges = <0x0 0x10000000 0x1FFFFF>;
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@ -20,8 +20,18 @@ config SYS_ICACHE_LINE_SIZE
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default 32
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config SYS_TEXT_BASE
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default 0x9c000000 if !SPL
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default 0x80200000 if SPL
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config SPL_TEXT_BASE
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default 0x9c000000
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config SPL_PAYLOAD
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default "u-boot-lzma.img" if SPL_LZMA
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config BUILD_TARGET
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default "u-boot-with-spl.bin" if SPL
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choice
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prompt "MediaTek MIPS SoC select"
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@ -34,6 +44,15 @@ config SOC_MT7628
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select PINCTRL_MT7628
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select MTK_SERIAL
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select SYSRESET_RESETCTL
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select SPL_SEPARATE_BSS if SPL
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select SPL_INIT_STACK_WITHOUT_MALLOC_F if SPL
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select SPL_LOADER_SUPPORT if SPL
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select SPL_OF_CONTROL if SPL_DM
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select SPL_SIMPLE_BUS if SPL_DM
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select SPL_DM_SERIAL if SPL_DM
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select SPL_CLK if SPL_DM && SPL_SERIAL_SUPPORT
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select SPL_SYSRESET if SPL_DM
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select SPL_OF_LIBFDT if SPL_OF_CONTROL
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help
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This supports MediaTek MT7628/MT7688.
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@ -88,6 +107,14 @@ endchoice
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config SUPPORTS_BOOT_RAM
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bool
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config SPL_UART2_SPIS_PINMUX
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bool "Use alternative pinmux for UART2 in SPL stage"
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depends on SPL_SERIAL_SUPPORT
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default n
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help
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Select this if the UART2 of your board is connected to GPIO 16/17
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(shared with SPIS) rather than the usual GPIO 20/21.
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source "board/gardena/smart-gateway-mt7688/Kconfig"
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source "board/seeed/linkit-smart-7688/Kconfig"
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@ -3,5 +3,6 @@
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obj-y += cpu.o
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obj-y += ddr_init.o
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obj-y += ddr_cal.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_SOC_MT7628) += mt7628/
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13
arch/mips/mach-mtmips/include/mach/serial.h
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13
arch/mips/mach-mtmips/include/mach/serial.h
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _MTMIPS_SERIAL_H_
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#define _MTMIPS_SERIAL_H_
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void mtmips_spl_serial_init(void);
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#endif /* _MTMIPS_SERIAL_H_ */
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@ -3,3 +3,4 @@
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obj-y += lowlevel_init.o
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obj-y += init.o
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obj-y += ddr.o
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obj-$(CONFIG_SPL_BUILD) += serial.o
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34
arch/mips/mach-mtmips/mt7628/serial.c
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34
arch/mips/mach-mtmips/mt7628/serial.c
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@ -0,0 +1,34 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include "mt7628.h"
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void mtmips_spl_serial_init(void)
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{
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#ifdef CONFIG_SPL_SERIAL_SUPPORT
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void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
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#if CONFIG_CONS_INDEX == 1
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clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M);
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#elif CONFIG_CONS_INDEX == 2
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clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M);
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#elif CONFIG_CONS_INDEX == 3
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setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M);
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#ifdef CONFIG_SPL_UART2_SPIS_PINMUX
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setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M);
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clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M,
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1 << UART2_MODE_S);
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#else
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clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M);
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clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M,
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1 << SPIS_MODE_S);
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#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */
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#endif /* CONFIG_CONS_INDEX */
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#endif /* CONFIG_SPL_SERIAL_SUPPORT */
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}
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44
arch/mips/mach-mtmips/spl.c
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44
arch/mips/mach-mtmips/spl.c
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@ -0,0 +1,44 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <common.h>
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#include <fdt.h>
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#include <spl.h>
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#include <asm/sections.h>
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#include <linux/sizes.h>
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#include <mach/serial.h>
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void __noreturn board_init_f(ulong dummy)
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{
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spl_init();
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#ifdef CONFIG_SPL_SERIAL_SUPPORT
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/*
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* mtmips_spl_serial_init() is useful if debug uart is enabled,
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* or DM based serial is not enabled.
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*/
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mtmips_spl_serial_init();
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preloader_console_init();
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#endif
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board_init_r(NULL, 0);
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}
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void board_boot_order(u32 *spl_boot_list)
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{
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spl_boot_list[0] = BOOT_DEVICE_NOR;
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}
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unsigned long spl_nor_get_uboot_base(void)
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{
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void *uboot_base = __image_copy_end;
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if (fdt_magic(uboot_base) == FDT_MAGIC)
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return (unsigned long)uboot_base + fdt_totalsize(uboot_base);
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return (unsigned long)uboot_base;
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}
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