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https://github.com/brain-hackers/u-boot-brain
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77efdeb758
The unmapped entries in tiler space are set with values 0xFF. So creating a DMM section of size 16MB at 0xFF000000 with ADDRSPACE set to 0x2. This way all the unmapped entry accesses to tiler will be trapped by the EMIF and a error response is sent to the L3 interconnect. L3 errors are inturn reported to MPU. Note that here the tiler trap section is overlapping with the actual ddr physical space and we lose 16MB out of the total 2GB. Signed-off-by: R Sricharan <r.sricharan@ti.com>
222 lines
6.1 KiB
C
222 lines
6.1 KiB
C
/*
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* Timing and Organization details of the ddr device parts used in OMAP5
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* EVM
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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* Sricharan R <r.sricharan@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/emif.h>
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#include <asm/arch/sys_proto.h>
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/*
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* This file provides details of the LPDDR2 SDRAM parts used on OMAP5
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* EVM. Since the parts used and geometry are identical for
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* evm for a given OMAP5 revision, this information is kept
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* here instead of being in board directory. However the key functions
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* exported are weakly linked so that they can be over-ridden in the board
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* directory if there is a OMAP5 board in the future that uses a different
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* memory device or geometry.
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*
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* For any new board with different memory devices over-ride one or more
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* of the following functions as per the CONFIG flags you intend to enable:
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* - emif_get_reg_dump()
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* - emif_get_dmm_regs()
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* - emif_get_device_details()
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* - emif_get_device_timings()
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*/
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#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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const struct emif_regs emif_regs_532_mhz_2cs = {
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.sdram_config_init = 0x80800EBA,
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.sdram_config = 0x808022BA,
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.ref_ctrl = 0x0000081A,
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.sdram_tim1 = 0x772F6873,
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.sdram_tim2 = 0x304a129a,
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.sdram_tim3 = 0x02f7e45f,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x000b3215,
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.temp_alert_config = 0x08000a05,
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.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
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.emif_ddr_phy_ctlr_1 = 0x0E28420d,
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.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
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.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
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.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
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.emif_ddr_ext_phy_ctrl_5 = 0x04010040
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};
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const struct emif_regs emif_regs_266_mhz_2cs = {
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.sdram_config_init = 0x80800EBA,
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.sdram_config = 0x808022BA,
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.ref_ctrl = 0x0000040D,
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.sdram_tim1 = 0x2A86B419,
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.sdram_tim2 = 0x1025094A,
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.sdram_tim3 = 0x026BA22F,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x000b3215,
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.temp_alert_config = 0x08000a05,
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.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
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.emif_ddr_phy_ctlr_1 = 0x0E28420d,
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.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
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.emif_ddr_ext_phy_ctrl_3 = 0x14829052,
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.emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
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.emif_ddr_ext_phy_ctrl_5 = 0x04010040
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};
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const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x80740300,
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.dmm_lisa_map_3 = 0xFF020100
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};
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const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
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0x01004010,
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0x00001004,
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0x04010040,
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0x01004010,
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0x00001004,
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0x00000000,
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0x00000000,
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0x00000000,
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0x80080080,
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0x00800800,
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0x08102040,
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0x00000001,
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0x540A8150,
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0xA81502a0,
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0x002A0540,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000077
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};
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static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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{
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*regs = &emif_regs_532_mhz_2cs;
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}
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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__attribute__((weak, alias("emif_get_reg_dump_sdp")));
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static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
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**dmm_lisa_regs)
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{
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*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
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}
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
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#else
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static const struct lpddr2_device_details dev_4G_S4_details = {
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.type = LPDDR2_TYPE_S4,
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.density = LPDDR2_DENSITY_4Gb,
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.io_width = LPDDR2_IO_WIDTH_32,
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.manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
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};
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static void emif_get_device_details_sdp(u32 emif_nr,
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struct lpddr2_device_details *cs0_device_details,
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struct lpddr2_device_details *cs1_device_details)
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{
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/* EMIF1 & EMIF2 have identical configuration */
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*cs0_device_details = dev_4G_S4_details;
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*cs1_device_details = dev_4G_S4_details;
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}
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void emif_get_device_details(u32 emif_nr,
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struct lpddr2_device_details *cs0_device_details,
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struct lpddr2_device_details *cs1_device_details)
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__attribute__((weak, alias("emif_get_device_details_sdp")));
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#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
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#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
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.max_freq = 532000000,
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.RL = 8,
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.tRPab = 21,
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.tRCD = 18,
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.tWR = 15,
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.tRASmin = 42,
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.tRRD = 10,
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.tWTRx2 = 15,
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.tXSR = 140,
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.tXPx2 = 15,
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.tRFCab = 130,
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.tRTPx2 = 15,
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.tCKE = 3,
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.tCKESR = 15,
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.tZQCS = 90,
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.tZQCL = 360,
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.tZQINIT = 1000,
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.tDQSCKMAXx2 = 11,
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.tRASmax = 70,
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.tFAW = 50
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};
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static const struct lpddr2_min_tck min_tck = {
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.tRL = 3,
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.tRP_AB = 3,
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.tRCD = 3,
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.tWR = 3,
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.tRAS_MIN = 3,
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.tRRD = 2,
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.tWTR = 2,
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.tXP = 2,
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.tRTP = 2,
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.tCKE = 3,
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.tCKESR = 3,
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.tFAW = 8
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};
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static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
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&timings_jedec_532_mhz
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};
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static const struct lpddr2_device_timings dev_4G_S4_timings = {
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.ac_timings = ac_timings,
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.min_tck = &min_tck,
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};
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void emif_get_device_timings_sdp(u32 emif_nr,
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const struct lpddr2_device_timings **cs0_device_timings,
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const struct lpddr2_device_timings **cs1_device_timings)
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{
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/* Identical devices on EMIF1 & EMIF2 */
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*cs0_device_timings = &dev_4G_S4_timings;
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*cs1_device_timings = &dev_4G_S4_timings;
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}
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void emif_get_device_timings(u32 emif_nr,
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const struct lpddr2_device_timings **cs0_device_timings,
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const struct lpddr2_device_timings **cs1_device_timings)
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__attribute__((weak, alias("emif_get_device_timings_sdp")));
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#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
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