mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 13:16:16 +09:00
7a4b6964b5
This patch adds SPL support for mtmips platform. The lowlevel architecture is split into SPL and the rest parts are built into a memory loadable u-boot image. Optional SPL_DM and OF_CONTROL are also supported. The increment of size is very small (< 10 KiB) if SPL_DM and OF_CONTROL are not enabled and the memory bootable u-boot (u-boot.img) is generated automatically so there is not need to add a separate config for it. A lzma compressed payload (u-boot-lzma.img) is also generated and it will be combined with u-boot-spl.bin to form the unified ROM bootable binary u-boot-mtmips.bin. A spl loader is added to support uncompress the payload. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
35 lines
1.0 KiB
C
35 lines
1.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2020 MediaTek Inc.
|
|
*
|
|
* Author: Weijie Gao <weijie.gao@mediatek.com>
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include "mt7628.h"
|
|
|
|
void mtmips_spl_serial_init(void)
|
|
{
|
|
#ifdef CONFIG_SPL_SERIAL_SUPPORT
|
|
void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
|
|
|
|
#if CONFIG_CONS_INDEX == 1
|
|
clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART0_MODE_M);
|
|
#elif CONFIG_CONS_INDEX == 2
|
|
clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART1_MODE_M);
|
|
#elif CONFIG_CONS_INDEX == 3
|
|
setbits_32(base + SYSCTL_AGPIO_CFG_REG, EPHY_GPIO_AIO_EN_M);
|
|
#ifdef CONFIG_SPL_UART2_SPIS_PINMUX
|
|
setbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M);
|
|
clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M,
|
|
1 << UART2_MODE_S);
|
|
#else
|
|
clrbits_32(base + SYSCTL_GPIO_MODE1_REG, UART2_MODE_M);
|
|
clrsetbits_32(base + SYSCTL_GPIO_MODE1_REG, SPIS_MODE_M,
|
|
1 << SPIS_MODE_S);
|
|
#endif /* CONFIG_SPL_UART2_SPIS_PINMUX */
|
|
#endif /* CONFIG_CONS_INDEX */
|
|
#endif /* CONFIG_SPL_SERIAL_SUPPORT */
|
|
}
|