mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
770ee01742
Add a device-tree property use-lvl-write-cache that will cause writes to lvl to be cached instead of read from lvl before each write. This is required on some platforms that have the register implemented as dual read/write (such as Baytrail). Prior to this fix the blue USB port on the Minnowboard Max was unusable since USB_HOST_EN0 was set high then immediately set low when USB_HOST_EN1 was written. This also resolves the 'gpio clear | set' command warning like: "Warning: value of pin is still 0" Signed-off-by: George McCollister <george.mccollister@gmail.com> <rebased on latest origin/master, fixed all baytrail boards> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
315 lines
7.1 KiB
Plaintext
315 lines
7.1 KiB
Plaintext
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/gpio/x86-gpio.h>
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#include <dt-bindings/interrupt-router/intel-irq.h>
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#include "skeleton.dtsi"
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#include "rtc.dtsi"
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#include "tsc_timer.dtsi"
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/ {
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config {
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silent_console = <0>;
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};
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pch_pinctrl {
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compatible = "intel,x86-pinctrl";
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reg = <0 0>;
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/* Add UART1 PAD configuration (SIO HS-UART) */
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uart1_txd@0 {
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pad-offset = <0x10>;
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mode-func = <1>;
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};
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uart1_rxd@0 {
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pad-offset = <0x20>;
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mode-func = <1>;
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};
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/*
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* As of today, the latest version FSP (gold4) for BayTrail
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* misses the PAD configuration of the SD controller's Card
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* Detect signal. The default PAD value for the CD pin sets
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* the pin to work in GPIO mode, which causes card detect
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* status cannot be reflected by the Present State register
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* in the SD controller (bit 16 & bit 18 are always zero).
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*
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* Configure this pin to function 1 (SD controller).
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*/
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sdmmc3_cd@0 {
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pad-offset = <0x3a0>;
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mode-func = <1>;
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};
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};
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chosen {
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stdout-path = "/serial";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <0>;
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intel,apic-id = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <1>;
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intel,apic-id = <2>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <2>;
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intel,apic-id = <4>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "intel,baytrail-cpu";
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reg = <3>;
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intel,apic-id = <6>;
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};
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};
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pci {
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compatible = "intel,pci-baytrail", "pci-x86";
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#address-cells = <3>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
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0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
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0x01000000 0x0 0x2000 0x2000 0 0xe000>;
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pciuart0: uart@1e,3 {
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compatible = "pci8086,0f0a.00",
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"pci8086,0f0a",
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"pciclass,070002",
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"pciclass,0700",
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"ns16550";
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u-boot,dm-pre-reloc;
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reg = <0x0200f310 0x0 0x0 0x0 0x0>;
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reg-shift = <2>;
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clock-frequency = <58982400>;
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current-speed = <115200>;
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};
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pch@1f,0 {
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reg = <0x0000f800 0 0 0 0>;
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compatible = "pci8086,0f1c", "intel,pch9";
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#address-cells = <1>;
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#size-cells = <1>;
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irq-router {
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compatible = "intel,irq-router";
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intel,pirq-config = "ibase";
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intel,ibase-offset = <0x50>;
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intel,actl-addr = <0>;
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intel,pirq-link = <8 8>;
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intel,pirq-mask = <0xdee0>;
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intel,pirq-routing = <
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/* BayTrail PCI devices */
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PCI_BDF(0, 2, 0) INTA PIRQA
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PCI_BDF(0, 3, 0) INTA PIRQA
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PCI_BDF(0, 16, 0) INTA PIRQA
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PCI_BDF(0, 17, 0) INTA PIRQA
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PCI_BDF(0, 18, 0) INTA PIRQA
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PCI_BDF(0, 19, 0) INTA PIRQA
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PCI_BDF(0, 20, 0) INTA PIRQA
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PCI_BDF(0, 21, 0) INTA PIRQA
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PCI_BDF(0, 22, 0) INTA PIRQA
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PCI_BDF(0, 23, 0) INTA PIRQA
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PCI_BDF(0, 24, 0) INTA PIRQA
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PCI_BDF(0, 24, 1) INTC PIRQC
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PCI_BDF(0, 24, 2) INTD PIRQD
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PCI_BDF(0, 24, 3) INTB PIRQB
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PCI_BDF(0, 24, 4) INTA PIRQA
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PCI_BDF(0, 24, 5) INTC PIRQC
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PCI_BDF(0, 24, 6) INTD PIRQD
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PCI_BDF(0, 24, 7) INTB PIRQB
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PCI_BDF(0, 26, 0) INTA PIRQA
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PCI_BDF(0, 27, 0) INTA PIRQA
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PCI_BDF(0, 28, 0) INTA PIRQA
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PCI_BDF(0, 28, 1) INTB PIRQB
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PCI_BDF(0, 28, 2) INTC PIRQC
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PCI_BDF(0, 28, 3) INTD PIRQD
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PCI_BDF(0, 29, 0) INTA PIRQA
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PCI_BDF(0, 30, 0) INTA PIRQA
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PCI_BDF(0, 30, 1) INTD PIRQD
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PCI_BDF(0, 30, 2) INTB PIRQB
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PCI_BDF(0, 30, 3) INTC PIRQC
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PCI_BDF(0, 30, 4) INTD PIRQD
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PCI_BDF(0, 30, 5) INTB PIRQB
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PCI_BDF(0, 31, 3) INTB PIRQB
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/*
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* PCIe root ports downstream
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* interrupts
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*/
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PCI_BDF(1, 0, 0) INTA PIRQA
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PCI_BDF(1, 0, 0) INTB PIRQB
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PCI_BDF(1, 0, 0) INTC PIRQC
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PCI_BDF(1, 0, 0) INTD PIRQD
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PCI_BDF(2, 0, 0) INTA PIRQB
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PCI_BDF(2, 0, 0) INTB PIRQC
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PCI_BDF(2, 0, 0) INTC PIRQD
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PCI_BDF(2, 0, 0) INTD PIRQA
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PCI_BDF(3, 0, 0) INTA PIRQC
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PCI_BDF(3, 0, 0) INTB PIRQD
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PCI_BDF(3, 0, 0) INTC PIRQA
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PCI_BDF(3, 0, 0) INTD PIRQB
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PCI_BDF(4, 0, 0) INTA PIRQD
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PCI_BDF(4, 0, 0) INTB PIRQA
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PCI_BDF(4, 0, 0) INTC PIRQB
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PCI_BDF(4, 0, 0) INTD PIRQC
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>;
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};
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spi: spi {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "intel,ich9-spi";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0>;
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compatible = "stmicro,n25q064a",
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"spi-flash";
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memory-map = <0xff800000 0x00800000>;
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rw-mrc-cache {
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label = "rw-mrc-cache";
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reg = <0x006f0000 0x00010000>;
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};
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};
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};
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gpioa {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0 0x20>;
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bank-name = "A";
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use-lvl-write-cache;
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};
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gpiob {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x20 0x20>;
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bank-name = "B";
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use-lvl-write-cache;
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};
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gpioc {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x40 0x20>;
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bank-name = "C";
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use-lvl-write-cache;
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};
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gpiod {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x60 0x20>;
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bank-name = "D";
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use-lvl-write-cache;
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};
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gpioe {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0x80 0x20>;
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bank-name = "E";
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use-lvl-write-cache;
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};
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gpiof {
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compatible = "intel,ich6-gpio";
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u-boot,dm-pre-reloc;
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reg = <0xA0 0x20>;
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bank-name = "F";
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use-lvl-write-cache;
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};
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};
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};
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fsp {
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compatible = "intel,baytrail-fsp";
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fsp,mrc-init-tseg-size = <0>;
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fsp,mrc-init-mmio-size = <0x800>;
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fsp,mrc-init-spd-addr1 = <0xa0>;
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fsp,mrc-init-spd-addr2 = <0xa2>;
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fsp,emmc-boot-mode = <1>;
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fsp,enable-sdio;
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fsp,enable-sdcard;
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fsp,enable-hsuart0;
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fsp,enable-hsuart1;
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fsp,enable-spi;
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fsp,enable-sata;
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fsp,sata-mode = <1>;
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fsp,enable-lpe;
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fsp,lpss-sio-enable-pci-mode;
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fsp,enable-dma0;
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fsp,enable-dma1;
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fsp,enable-i2c0;
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fsp,enable-i2c1;
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fsp,enable-i2c2;
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fsp,enable-i2c3;
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fsp,enable-i2c4;
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fsp,enable-i2c5;
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fsp,enable-i2c6;
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fsp,enable-pwm0;
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fsp,enable-pwm1;
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fsp,igd-dvmt50-pre-alloc = <2>;
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fsp,aperture-size = <2>;
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fsp,gtt-size = <2>;
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fsp,scc-enable-pci-mode;
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fsp,os-selection = <4>;
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fsp,emmc45-ddr50-enabled;
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fsp,emmc45-retune-timer-value = <8>;
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fsp,enable-igd;
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fsp,enable-memory-down;
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fsp,memory-down-params {
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compatible = "intel,baytrail-fsp-mdp";
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fsp,dram-speed = <2>; /* 2=1333MHz */
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fsp,dram-type = <1>; /* 1=DDR3L */
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fsp,dimm-0-enable;
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fsp,dimm-width = <1>; /* 1=x16, 2=x32 */
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fsp,dimm-density = <3>; /* 3=8Gbit */
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fsp,dimm-bus-width = <3>; /* 3=64bits */
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fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */
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/* These following values might need a re-visit */
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fsp,dimm-tcl = <8>;
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fsp,dimm-trpt-rcd = <8>;
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fsp,dimm-twr = <8>;
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fsp,dimm-twtr = <4>;
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fsp,dimm-trrd = <6>;
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fsp,dimm-trtp = <4>;
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fsp,dimm-tfaw = <22>;
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};
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};
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microcode {
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update@0 {
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#include "microcode/m0130673325.dtsi"
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};
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update@1 {
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#include "microcode/m0130679907.dtsi"
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};
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};
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};
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