u-boot-brain/arch/x86/dts
Bin Meng 770ee01742 x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode
Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).

Prior to this fix the blue USB port on the Minnowboard Max was
unusable since USB_HOST_EN0 was set high then immediately set
low when USB_HOST_EN1 was written.

This also resolves the 'gpio clear | set' command warning like:
  "Warning: value of pin is still 0"

Signed-off-by: George McCollister <george.mccollister@gmail.com>
<rebased on latest origin/master, fixed all baytrail boards>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-05-17 17:13:06 +08:00
..
include Makefile: Support include files for .dts files 2014-06-20 11:55:03 -06:00
microcode x86: Use latest microcode for all BayTrail boards 2016-05-23 15:26:46 +08:00
.gitignore dts: generate multiple device tree blobs 2014-02-19 11:10:05 -05:00
bayleybay.dts x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode 2017-05-17 17:13:06 +08:00
baytrail_som-db5800-som-6867.dts x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode 2017-05-17 17:13:06 +08:00
broadwell_som-6896.dts x86: coreboot: Convert to use DM coreboot video driver 2016-10-12 10:58:24 +08:00
chromebook_link.dts x86: link: Set up device tree for SPL 2017-02-07 13:10:59 +08:00
chromebook_samus.dts x86: coreboot: Convert to use DM coreboot video driver 2016-10-12 10:58:24 +08:00
chromebox_panther.dts x86: coreboot: Convert to use DM coreboot video driver 2016-10-12 10:58:24 +08:00
conga-qeval20-qa3-e3845.dts x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode 2017-05-17 17:13:06 +08:00
coreboot_fb.dtsi x86: coreboot: Convert to use DM coreboot video driver 2016-10-12 10:58:24 +08:00
cougarcanyon2.dts x86: Add Intel Cougar Canyon 2 board 2016-02-21 13:42:52 +08:00
crownbay.dts x86: dts: Update to include ACTL register details 2016-05-23 15:18:00 +08:00
dfi-bt700-q7x-151.dts x86: Add DFI BT700 BayTrail board support 2016-08-16 11:44:09 +08:00
dfi-bt700.dtsi x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode 2017-05-17 17:13:06 +08:00
efi.dts x86: Convert to use driver model timer 2015-12-01 06:26:35 -07:00
emulation-u-boot.dtsi x86: qemu: Mark ucode as optional for SPL in u-boot.dtsi 2017-02-07 13:27:13 +08:00
galileo.dts x86: galileo: Enable CPU driver 2016-05-23 15:27:41 +08:00
keyboard.dtsi x86: Add an i8042 device for boards that have it 2015-11-19 20:13:41 -07:00
Makefile x86: Add theadorable-x86-dfi-bt700 board support 2016-08-16 11:44:09 +08:00
minnowmax.dts x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode 2017-05-17 17:13:06 +08:00
qemu-x86_i440fx.dts x86: qemu: Set up device tree for SPL 2017-02-07 13:27:11 +08:00
qemu-x86_q35.dts x86: qemu: Set up device tree for SPL 2017-02-07 13:27:11 +08:00
quark-u-boot.dtsi x86: quark: Fix build error for quark-based boards 2016-12-26 13:36:18 +08:00
rtc.dtsi x86: Enable DM RTC support for all x86 boards 2015-07-28 10:36:22 -06:00
serial.dtsi x86: dts: Mark serial as needed before relocation 2017-02-06 11:38:46 +08:00
skeleton.dtsi x86: fdt: Create basic .dtsi file for coreboot 2012-12-06 14:30:42 -08:00
theadorable-x86-dfi-bt700.dts x86: Add theadorable-x86-dfi-bt700 board support 2016-08-16 11:44:09 +08:00
tsc_timer.dtsi x86: Convert to use driver model timer 2015-12-01 06:26:35 -07:00
u-boot.dtsi x86: Add file names from Kconfig in descriptor/intel-me nodes in u-boot.dtsi 2017-04-10 10:02:03 +08:00