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https://github.com/brain-hackers/u-boot-brain
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![Mario Six](/assets/img/avatar_default.png)
Import the Linux device tree for the Gazerbeam board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
186 lines
2.8 KiB
Plaintext
186 lines
2.8 KiB
Plaintext
/*
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* Gazerbeam Device Tree Source
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*
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* (C) Copyright 2015
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "gdsys,gazerbeam";
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compatible = "fsl,mpc8308rdb";
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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};
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memory {
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device_type = "memory";
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};
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};
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&enet1 {
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status = "okay";
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};
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&IIC {
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fsl,preserve-clocking;
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at97sc3205t@29 {
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compatible = "atmel,at97sc3204t";
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reg = <0x29>;
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};
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lm77@48 {
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compatible = "national,lm77";
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reg = <0x48>;
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};
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ads1015@49 {
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compatible = "ti,ads1015";
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reg = <0x49>;
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};
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lm77@4a {
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compatible = "national,lm77";
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reg = <0x4a>;
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};
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emc2305@2e {
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compatible = "smsc,emc2305";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2e>;
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fan@0 {
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reg = <0>;
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};
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fan@1 {
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reg = <1>;
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};
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fan@2 {
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reg = <2>;
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};
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fan@3 {
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reg = <3>;
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};
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fan@4 {
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reg = <4>;
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};
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};
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emc2305@4c {
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compatible = "smsc,emc2305";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x4c>;
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fan@0 {
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reg = <0>;
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};
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fan@1 {
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reg = <1>;
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};
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fan@2 {
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reg = <2>;
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};
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fan@3 {
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reg = <3>;
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};
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fan@4 {
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reg = <4>;
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};
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};
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at24c512@54 {
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compatible = "atmel,24c512";
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reg = <0x54>;
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};
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/* PPC-Board */
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pca9698@22 {
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compatible = "nxp,pca9698";
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reg = <0x22>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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/* IO-Board */
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pca9698@20 {
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compatible = "nxp,pca9698";
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reg = <0x20>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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&IIC2 {
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fsl,preserve-clocking;
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status = "okay";
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/* MC2/SC-Board */
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GPIO_VB0: pca9698@20 {
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compatible = "nxp,pca9698";
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reg = <0x20>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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/* MC4-Board */
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GPIO_VB1: pca9698@22 {
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compatible = "nxp,pca9698";
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reg = <0x22>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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};
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&SPI {
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gpios = < /*SPI-CSS-FPGA-U-FLASH#*/ &gpio0 8 0
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/*SPI-CSS-FPGA-O-FLASH#*/ &gpio0 6 0
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/*SPI-CSS-STDP1_U-FLASH#*/ &gpio0 12 0
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/*SPI-CSS-STDP2_U-FLASH#*/ &gpio0 11 0
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/*SPI-CSS-STDP1_O-FLASH#*/ &gpio0 15 0
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/*SPI-CSS-STDP2_O-FLASH#*/ &gpio0 3 0>;
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m25p16@0 {
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compatible = "st,n25q128a11";
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reg = <0x0>;
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spi-max-frequency = <20000000>;
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};
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m25p16@1 {
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compatible = "st,n25q128a11";
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reg = <0x1>;
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spi-max-frequency = <20000000>;
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};
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m25p16@2 {
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compatible = "st,m25p40";
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reg = <0x2>;
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spi-max-frequency = <20000000>;
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};
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m25p16@3 {
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compatible = "st,m25p40";
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reg = <0x3>;
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spi-max-frequency = <20000000>;
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};
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m25p16@4 {
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compatible = "st,m25p40";
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reg = <0x4>;
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spi-max-frequency = <20000000>;
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};
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m25p16@5 {
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compatible = "st,m25p40";
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reg = <0x5>;
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spi-max-frequency = <20000000>;
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};
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};
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