Ian Campbell 21f0fd245e jetson-tk1: Add PSCI configuration options and reserve secure code ... The secure world code is relocated to the MB just below the top of 4G, we reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is not protected in h/w. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>		2015-05-13 09:24:16 -07:00
..
clock.c	tegra124: clock: Add display clocks and functions	2015-05-13 09:24:09 -07:00
cpu.c	ARM: tegra: collect SoC sources into mach-tegra	2015-02-21 08:23:51 -05:00
funcmux.c	ARM: tegra: collect SoC sources into mach-tegra	2015-02-21 08:23:51 -05:00
Kconfig	jetson-tk1: Add PSCI configuration options and reserve secure code	2015-05-13 09:24:16 -07:00
Makefile	tegra124: Add PSCI support for Tegra124	2015-05-13 09:24:15 -07:00
pinmux.c	ARM: tegra: enable MIPI PAD CTRL support for Tegra124	2015-03-30 09:54:06 -07:00
psci.c	tegra124: Add PSCI support for Tegra124	2015-05-13 09:24:15 -07:00
xusb-padctl.c	ARM: tegra: collect SoC sources into mach-tegra	2015-02-21 08:23:51 -05:00