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https://github.com/brain-hackers/u-boot-brain
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tegra124: clock: Add display clocks and functions
Add functions to provide access to the display clocks on Tegra124 including setting the clock rate for an EDP display. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Simon Glass
Tom Warren
parent
7bb6199bd6
commit
96e82a253a
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@ -202,9 +202,13 @@ struct clk_rst_ctlr {
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uint crc_reserved52[1]; /* _reserved_52, 0x554 */
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uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
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uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */
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/* Tegra124 - skip to 0x600 here for new CLK_SOURCE_ regs */
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uint crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */
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u32 _rsv32[4]; /* 0x560-0x56c */
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u32 crc_plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */
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u32 _rsv32_1[7]; /* 0x574-58c */
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struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
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u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
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u32 _rsrv32_2[25];
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/* Tegra124 */
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uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
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};
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@ -440,4 +444,9 @@ enum {
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#define PLLX_IDDQ_SHIFT 3
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#define PLLX_IDDQ_MASK (1U << PLLX_IDDQ_SHIFT)
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/* CLK_RST_PLLDP_SS_CFG */
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#define PLLDP_SS_CFG_CLAMP (1 << 22)
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#define PLLDP_SS_CFG_UNDOCUMENTED (1 << 24)
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#define PLLDP_SS_CFG_DITHER (1 << 28)
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#endif /* _TEGRA_CLK_RST_H_ */
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@ -25,6 +25,7 @@ enum clock_id {
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CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
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CLOCK_ID_EPCI,
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CLOCK_ID_SFROM32KHZ,
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CLOCK_ID_DP, /* Special for Tegra124 */
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/* These are the base clocks (inputs to the Tegra SoC) */
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CLOCK_ID_32KHZ,
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@ -424,7 +425,7 @@ enum periphc_internal_id {
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/* 0x58 */
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PERIPHC_58h,
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PERIPHC_59h,
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PERIPHC_SOR,
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PERIPHC_5ah,
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PERIPHC_5bh,
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PERIPHC_SATAOOB,
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@ -16,6 +16,27 @@
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#define OSC_FREQ_SHIFT 28
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#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
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/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
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#define SOR0_CLK_SEL0 (1 << 14)
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#define SOR0_CLK_SEL1 (1 << 15)
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int tegra_plle_enable(void);
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void clock_sor_enable_edp_clock(void);
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/**
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* clock_set_display_rate() - Set the display clock rate
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*
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* @frequency: the requested PLLD frequency
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*
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* Return the PLLD frequenc (which may not quite what was requested), or 0
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* on failure
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*/
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u32 clock_set_display_rate(u32 frequency);
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/**
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* clock_set_up_plldp() - Set up the EDP clock ready for use
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*/
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void clock_set_up_plldp(void);
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#endif /* _TEGRA124_CLOCK_H_ */
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@ -593,6 +593,7 @@ void clock_init(void)
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pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
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pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
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pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
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pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
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pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
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pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
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pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
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@ -600,6 +601,7 @@ void clock_init(void)
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debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
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debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
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debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
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debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
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debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
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/* Do any special system timer/TSC setup */
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@ -42,6 +42,7 @@ enum clock_type_id {
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CLOCK_TYPE_ASPTE,
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CLOCK_TYPE_PMDACD2T,
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CLOCK_TYPE_PCST,
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CLOCK_TYPE_DP,
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CLOCK_TYPE_PC2CC3M,
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CLOCK_TYPE_PC2CC3S_T,
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@ -101,6 +102,10 @@ static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX+1] = {
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{ CLK(PERIPH), CLK(CGENERAL), CLK(SFROM32KHZ), CLK(OSC),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_28},
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/* CLOCK_TYPE_DP */
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{ CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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CLK(NONE), CLK(NONE), CLK(NONE), CLK(NONE),
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MASK_BITS_31_28},
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/* Additional clock types on Tegra114+ */
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/* CLOCK_TYPE_PC2CC3M */
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@ -259,7 +264,7 @@ static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
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/* 0x58 */
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TYPE(PERIPHC_58h, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_59h, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SOR, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_5ah, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_5bh, CLOCK_TYPE_NONE),
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TYPE(PERIPHC_SATAOOB, CLOCK_TYPE_PCMT),
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@ -546,7 +551,7 @@ static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
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NONE(X_RESERVED19),
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NONE(ADX1),
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NONE(DPAUX),
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NONE(SOR0),
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PERIPHC_SOR,
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NONE(X_RESERVED23),
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/* 184 */
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@ -594,7 +599,10 @@ u32 *get_periph_source_reg(enum periph_id periph_id)
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assert(periph_id >= PERIPH_ID_FIRST && periph_id < PERIPH_ID_COUNT);
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internal_id = periph_id_to_internal_id[periph_id];
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assert(internal_id != -1);
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if (internal_id >= PERIPHC_VW_FIRST) {
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if (internal_id >= PERIPHC_X_FIRST) {
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internal_id -= PERIPHC_X_FIRST;
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return &clkrst->crc_clk_src_x[internal_id];
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} else if (internal_id >= PERIPHC_VW_FIRST) {
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internal_id -= PERIPHC_VW_FIRST;
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return &clkrst->crc_clk_src_vw[internal_id];
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} else {
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@ -657,8 +665,10 @@ void clock_set_enable(enum periph_id periph_id, int enable)
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assert(clock_periph_id_isvalid(periph_id));
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if ((int)periph_id < (int)PERIPH_ID_VW_FIRST)
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clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
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else
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else if ((int)periph_id < PERIPH_ID_X_FIRST)
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clk = &clkrst->crc_clk_out_enb_vw[PERIPH_REG(periph_id)];
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else
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clk = &clkrst->crc_clk_out_enb_x;
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reg = readl(clk);
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if (enable)
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reg |= PERIPH_MASK(periph_id);
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@ -678,8 +688,10 @@ void reset_set_enable(enum periph_id periph_id, int enable)
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assert(clock_periph_id_isvalid(periph_id));
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if (periph_id < PERIPH_ID_VW_FIRST)
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reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
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else
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else if ((int)periph_id < PERIPH_ID_X_FIRST)
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reset = &clkrst->crc_rst_dev_vw[PERIPH_REG(periph_id)];
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else
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reset = &clkrst->crc_rst_devices_x;
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reg = readl(reset);
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if (enable)
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reg |= PERIPH_MASK(periph_id);
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@ -933,3 +945,122 @@ int tegra_plle_enable(void)
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return 0;
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}
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void clock_sor_enable_edp_clock(void)
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{
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u32 *reg;
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/* uses PLLP, has a non-standard bit layout. */
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reg = get_periph_source_reg(PERIPH_ID_SOR0);
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setbits_le32(reg, SOR0_CLK_SEL0);
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}
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u32 clock_set_display_rate(u32 frequency)
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{
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/**
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* plld (fo) = vco >> p, where 500MHz < vco < 1000MHz
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* = (cf * n) >> p, where 1MHz < cf < 6MHz
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* = ((ref / m) * n) >> p
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*
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* Iterate the possible values of p (3 bits, 2^7) to find out a minimum
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* safe vco, then find best (m, n). since m has only 5 bits, we can
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* iterate all possible values. Note Tegra 124 supports 11 bits for n,
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* but our pll_fields has only 10 bits for n.
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*
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* Note values undershoot or overshoot target output frequency may not
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* work if the values are not in "safe" range by panel specification.
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*/
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u32 ref = clock_get_rate(CLOCK_ID_OSC);
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u32 divm, divn, divp, cpcon;
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u32 cf, vco, rounded_rate = frequency;
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u32 diff, best_diff, best_m = 0, best_n = 0, best_p;
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const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3,
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mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz,
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min_cf = 1 * mhz, max_cf = 6 * mhz;
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int mux_bits, divider_bits, source;
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for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++)
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vco <<= 1;
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if (vco < min_vco || vco > max_vco) {
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printf("%s: Cannot find out a supported VCO for Frequency (%u)\n",
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__func__, frequency);
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return 0;
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}
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best_p = divp;
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best_diff = vco;
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for (divm = 1; divm < max_m && best_diff; divm++) {
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cf = ref / divm;
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if (cf < min_cf)
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break;
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if (cf > max_cf)
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continue;
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divn = vco / cf;
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if (divn >= max_n)
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continue;
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diff = vco - divn * cf;
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if (divn + 1 < max_n && diff > cf / 2) {
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divn++;
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diff = cf - diff;
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}
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if (diff >= best_diff)
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continue;
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best_diff = diff;
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best_m = divm;
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best_n = divn;
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}
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if (best_n < 50)
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cpcon = 2;
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else if (best_n < 300)
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cpcon = 3;
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else if (best_n < 600)
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cpcon = 8;
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else
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cpcon = 12;
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if (best_diff) {
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printf("%s: Failed to match output frequency %u, best difference is %u\n",
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__func__, frequency, best_diff);
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rounded_rate = (ref / best_m * best_n) >> best_p;
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}
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debug("%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n",
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__func__, rounded_rate, ref, best_m, best_n, best_p, cpcon);
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source = get_periph_clock_source(PERIPH_ID_DISP1, CLOCK_ID_DISPLAY,
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&mux_bits, ÷r_bits);
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clock_ll_set_source_bits(PERIPH_ID_DISP1, mux_bits, source);
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clock_set_rate(CLOCK_ID_DISPLAY, best_n, best_m, best_p, cpcon);
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return rounded_rate;
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}
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void clock_set_up_plldp(void)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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u32 value;
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value = PLLDP_SS_CFG_UNDOCUMENTED | PLLDP_SS_CFG_DITHER;
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writel(value | PLLDP_SS_CFG_CLAMP, &clkrst->crc_plldp_ss_cfg);
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clock_start_pll(CLOCK_ID_DP, 1, 90, 3, 0, 0);
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writel(value, &clkrst->crc_plldp_ss_cfg);
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}
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struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
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{
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struct clk_rst_ctlr *clkrst =
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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if (clkid == CLOCK_ID_DP)
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return &clkrst->plldp;
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return NULL;
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}
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