mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 04:18:51 +09:00
![Peng Fan](/assets/img/avatar_default.png)
Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to DRAM. The boot log with Arm trusted firmware console enabled: " U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) PMIC: PFUZE100 ID=0x10 Normal Boot Trying to boot from MMC2 NOTICE: Configureing TZASC380 NOTICE: BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty NOTICE: BL31: Built : 09:28:54, Nov 8 2018 lpddr4 swffc start NOTICE: sip svc init U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800) CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz Reset cause: POR Model: Freescale i.MX8MQ EVK DRAM: 3 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial Net: Warning: ethernet@30be0000 using MAC address from ROM eth0: ethernet@30be0000 Hit any key to stop autoboot: 0 " Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
415 lines
9.7 KiB
Plaintext
415 lines
9.7 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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/dts-v1/;
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/* First 128KB is for PSCI ATF. */
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/memreserve/ 0x40000000 0x00020000;
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#include "fsl-imx8mq.dtsi"
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/ {
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model = "Freescale i.MX8MQ EVK";
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compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
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chosen {
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bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usdhc2_vmmc: usdhc2_vmmc {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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};
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pwmleds {
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compatible = "pwm-leds";
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ledpwm2 {
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label = "PWM2";
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pwms = <&pwm2 0 50000>;
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max-brightness = <255>;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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imx8mq-evk {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
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MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
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>;
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};
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pinctrl_pwm2: pwm2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
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MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
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MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
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MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
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MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
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MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
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MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2grpgpio {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
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MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
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fsl,pins = <
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MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
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MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
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MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
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MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
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MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
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MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
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MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_sai2: sai2grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
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MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
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MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
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MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
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MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
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>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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at803x,led-act-blind-workaround;
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at803x,eee-disabled;
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic: pfuze100@08 {
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compatible = "fsl,pfuze100";
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reg = <0x08>;
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regulators {
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sw1a_reg: sw1ab {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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sw1c_reg: sw1c {
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regulator-min-microvolt = <300000>;
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regulator-max-microvolt = <1875000>;
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regulator-always-on;
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};
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sw2_reg: sw2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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sw3a_reg: sw3ab {
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regulator-min-microvolt = <400000>;
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regulator-max-microvolt = <1975000>;
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regulator-always-on;
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};
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sw4_reg: sw4 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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swbst_reg: swbst {
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5150000>;
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};
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snvs_reg: vsnvs {
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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vref_reg: vrefddr {
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regulator-always-on;
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};
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vgen1_reg: vgen1 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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};
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vgen2_reg: vgen2 {
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1550000>;
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regulator-always-on;
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};
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vgen3_reg: vgen3 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen4_reg: vgen4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen5_reg: vgen5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-always-on;
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};
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vgen6_reg: vgen6 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "disabled";
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};
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&pwm2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm2>;
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status = "okay";
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};
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&lcdif {
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status = "okay";
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disp-dev = "mipi_dsi_northwest";
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display = <&display0>;
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display0: display@0 {
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bits-per-pixel = <24>;
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bus-width = <24>;
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <9200000>;
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hactive = <480>;
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vactive = <272>;
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hfront-porch = <8>;
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hback-porch = <4>;
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hsync-len = <41>;
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vback-porch = <2>;
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vfront-porch = <4>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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};
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};
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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flash0: n25q256a@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "micron,n25q256a";
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spi-max-frequency = <29000000>;
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spi-nor,ddr-quad-read-dummy = <6>;
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};
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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