mirror of
https://github.com/brain-hackers/u-boot-brain
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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
353 lines
9.7 KiB
C
353 lines
9.7 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#if defined(CONFIG_440)
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#include <ppc440.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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typedef struct region {
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u64 base;
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u32 size;
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u32 tlb_word2_i_value;
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} region_t;
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void remove_tlb(u32 vaddr, u32 size)
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{
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int i;
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u32 tlb_word0_value;
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u32 tlb_vaddr;
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u32 tlb_size = 0;
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for (i=0; i<PPC4XX_TLB_SIZE; i++) {
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tlb_word0_value = mftlb1(i);
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tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
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if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
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(tlb_vaddr >= vaddr)) {
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/*
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* TLB is enabled and start address is lower or equal
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* than the area we are looking for. Now we only have
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* to check the size/end address for a match.
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*/
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switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
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case TLB_WORD0_SIZE_1KB:
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tlb_size = 1 << 10;
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break;
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case TLB_WORD0_SIZE_4KB:
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tlb_size = 4 << 10;
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break;
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case TLB_WORD0_SIZE_16KB:
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tlb_size = 16 << 10;
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break;
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case TLB_WORD0_SIZE_64KB:
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tlb_size = 64 << 10;
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break;
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case TLB_WORD0_SIZE_256KB:
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tlb_size = 256 << 10;
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break;
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case TLB_WORD0_SIZE_1MB:
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tlb_size = 1 << 20;
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break;
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case TLB_WORD0_SIZE_16MB:
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tlb_size = 16 << 20;
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break;
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case TLB_WORD0_SIZE_256MB:
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tlb_size = 256 << 20;
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break;
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}
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/*
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* Now check the end-address if it's in the range
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*/
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if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1))
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/*
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* Found a TLB in the range.
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* Disable it by writing 0 to tlb0 word.
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*/
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mttlb1(i, 0);
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}
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}
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/* Execute an ISYNC instruction so that the new TLB entry takes effect */
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asm("isync");
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}
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/*
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* Change the I attribute (cache inhibited) of a TLB or multiple TLB's.
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* This function is used to either turn cache on or off in a specific
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* memory area.
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*/
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void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
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{
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int i;
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u32 tlb_word0_value;
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u32 tlb_word2_value;
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u32 tlb_vaddr;
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u32 tlb_size = 0;
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for (i=0; i<PPC4XX_TLB_SIZE; i++) {
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tlb_word0_value = mftlb1(i);
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tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
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if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
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(tlb_vaddr >= vaddr)) {
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/*
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* TLB is enabled and start address is lower or equal
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* than the area we are looking for. Now we only have
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* to check the size/end address for a match.
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*/
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switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
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case TLB_WORD0_SIZE_1KB:
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tlb_size = 1 << 10;
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break;
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case TLB_WORD0_SIZE_4KB:
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tlb_size = 4 << 10;
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break;
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case TLB_WORD0_SIZE_16KB:
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tlb_size = 16 << 10;
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break;
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case TLB_WORD0_SIZE_64KB:
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tlb_size = 64 << 10;
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break;
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case TLB_WORD0_SIZE_256KB:
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tlb_size = 256 << 10;
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break;
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case TLB_WORD0_SIZE_1MB:
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tlb_size = 1 << 20;
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break;
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case TLB_WORD0_SIZE_16MB:
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tlb_size = 16 << 20;
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break;
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case TLB_WORD0_SIZE_256MB:
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tlb_size = 256 << 20;
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break;
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}
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/*
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* Now check the end-address if it's in the range
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*/
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if (((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) ||
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((tlb_vaddr < (vaddr + size - 1)) &&
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((tlb_vaddr + tlb_size - 1) > (vaddr + size - 1)))) {
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/*
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* Found a TLB in the range.
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* Change cache attribute in tlb2 word.
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*/
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tlb_word2_value =
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TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
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TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
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TLB_WORD2_W_DISABLE | tlb_word2_i_value |
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TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
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TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
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TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
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TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
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TLB_WORD2_SR_ENABLE;
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/*
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* Now either flush or invalidate the dcache
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*/
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if (tlb_word2_i_value)
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flush_dcache();
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else
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invalidate_dcache();
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mttlb3(i, tlb_word2_value);
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asm("iccci 0,0");
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}
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}
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}
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/* Execute an ISYNC instruction so that the new TLB entry takes effect */
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asm("isync");
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}
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static int add_tlb_entry(u64 phys_addr,
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u32 virt_addr,
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u32 tlb_word0_size_value,
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u32 tlb_word2_i_value)
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{
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int i;
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unsigned long tlb_word0_value;
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unsigned long tlb_word1_value;
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unsigned long tlb_word2_value;
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/* First, find the index of a TLB entry not being used */
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for (i=0; i<PPC4XX_TLB_SIZE; i++) {
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tlb_word0_value = mftlb1(i);
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if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
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break;
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}
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if (i >= PPC4XX_TLB_SIZE)
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return -1;
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/* Second, create the TLB entry */
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tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
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TLB_WORD0_TS_0 | tlb_word0_size_value;
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tlb_word1_value = TLB_WORD1_RPN_ENCODE((u32)phys_addr) |
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TLB_WORD1_ERPN_ENCODE(phys_addr >> 32);
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tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
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TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
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TLB_WORD2_W_DISABLE | tlb_word2_i_value |
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TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
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TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
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TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
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TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
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TLB_WORD2_SR_ENABLE;
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/* Wait for all memory accesses to complete */
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sync();
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/* Third, add the TLB entries */
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mttlb1(i, tlb_word0_value);
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mttlb2(i, tlb_word1_value);
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mttlb3(i, tlb_word2_value);
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/* Execute an ISYNC instruction so that the new TLB entry takes effect */
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asm("isync");
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return 0;
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}
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static void program_tlb_addr(u64 phys_addr,
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u32 virt_addr,
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u32 mem_size,
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u32 tlb_word2_i_value)
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{
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int rc;
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int tlb_i;
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tlb_i = tlb_word2_i_value;
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while (mem_size != 0) {
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rc = 0;
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/* Add the TLB entries in to map the region. */
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if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
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(mem_size >= TLB_256MB_SIZE)) {
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/* Add a 256MB TLB entry */
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if ((rc = add_tlb_entry(phys_addr, virt_addr,
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TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
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mem_size -= TLB_256MB_SIZE;
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phys_addr += TLB_256MB_SIZE;
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virt_addr += TLB_256MB_SIZE;
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}
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} else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
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(mem_size >= TLB_16MB_SIZE)) {
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/* Add a 16MB TLB entry */
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if ((rc = add_tlb_entry(phys_addr, virt_addr,
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TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
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mem_size -= TLB_16MB_SIZE;
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phys_addr += TLB_16MB_SIZE;
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virt_addr += TLB_16MB_SIZE;
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}
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} else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
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(mem_size >= TLB_1MB_SIZE)) {
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/* Add a 1MB TLB entry */
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if ((rc = add_tlb_entry(phys_addr, virt_addr,
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TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
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mem_size -= TLB_1MB_SIZE;
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phys_addr += TLB_1MB_SIZE;
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virt_addr += TLB_1MB_SIZE;
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}
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} else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
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(mem_size >= TLB_256KB_SIZE)) {
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/* Add a 256KB TLB entry */
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if ((rc = add_tlb_entry(phys_addr, virt_addr,
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TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
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mem_size -= TLB_256KB_SIZE;
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phys_addr += TLB_256KB_SIZE;
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virt_addr += TLB_256KB_SIZE;
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}
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} else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
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(mem_size >= TLB_64KB_SIZE)) {
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/* Add a 64KB TLB entry */
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if ((rc = add_tlb_entry(phys_addr, virt_addr,
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TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
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mem_size -= TLB_64KB_SIZE;
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phys_addr += TLB_64KB_SIZE;
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virt_addr += TLB_64KB_SIZE;
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}
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} else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
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(mem_size >= TLB_16KB_SIZE)) {
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/* Add a 16KB TLB entry */
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if ((rc = add_tlb_entry(phys_addr, virt_addr,
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TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
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mem_size -= TLB_16KB_SIZE;
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phys_addr += TLB_16KB_SIZE;
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virt_addr += TLB_16KB_SIZE;
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}
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} else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
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(mem_size >= TLB_4KB_SIZE)) {
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/* Add a 4KB TLB entry */
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if ((rc = add_tlb_entry(phys_addr, virt_addr,
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TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
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mem_size -= TLB_4KB_SIZE;
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phys_addr += TLB_4KB_SIZE;
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virt_addr += TLB_4KB_SIZE;
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}
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} else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
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(mem_size >= TLB_1KB_SIZE)) {
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/* Add a 1KB TLB entry */
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if ((rc = add_tlb_entry(phys_addr, virt_addr,
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TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
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mem_size -= TLB_1KB_SIZE;
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phys_addr += TLB_1KB_SIZE;
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virt_addr += TLB_1KB_SIZE;
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}
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} else {
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printf("ERROR: no TLB size exists for the base address 0x%llx.\n",
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phys_addr);
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}
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if (rc != 0)
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printf("ERROR: no TLB entries available for the base addr 0x%llx.\n",
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phys_addr);
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}
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return;
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}
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/*
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* Program one (or multiple) TLB entries for one memory region
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*
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* Common usage for boards with SDRAM DIMM modules to dynamically
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* configure the TLB's for the SDRAM
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*/
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void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
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{
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region_t region_array;
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region_array.base = phys_addr;
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region_array.size = size;
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region_array.tlb_word2_i_value = tlb_word2_i_value; /* en-/disable cache */
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/* Call the routine to add in the tlb entries for the memory regions */
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program_tlb_addr(region_array.base, virt_addr, region_array.size,
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region_array.tlb_word2_i_value);
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return;
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}
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#endif /* CONFIG_440 */
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