mirror of
https://github.com/brain-hackers/u-boot-brain
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a47a12becf
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
236 lines
4.9 KiB
ArmAsm
236 lines
4.9 KiB
ArmAsm
/*
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* This file contains miscellaneous low-level functions.
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
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* and Paul Mackerras.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <config.h>
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#include <config.h>
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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/*
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* Flush instruction cache.
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*/
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_GLOBAL(invalidate_icache)
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iccci r0,r0
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isync
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blr
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/*
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* Write any modified data cache blocks out to memory
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* and invalidate the corresponding instruction cache blocks.
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*
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* flush_icache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_icache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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mr r6,r3
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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mtctr r4
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2: icbi 0,r6
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addi r6,r6,L1_CACHE_BYTES
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bdnz 2b
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sync /* additional sync needed on g4 */
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isync
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blr
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/*
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* Write any modified data cache blocks out to memory.
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* Does not invalidate the corresponding cache lines (especially for
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* any corresponding instruction cache).
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*
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* clean_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(clean_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbst 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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blr
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/*
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* Write any modified data cache blocks out to memory and invalidate them.
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* Does not invalidate the corresponding instruction cache blocks.
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*
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* flush_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(flush_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbf 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbst's to get to ram */
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blr
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/*
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* Like above, but invalidate the D-cache. This is used by the 8xx
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* to invalidate the cache so the PPC core doesn't get stale data
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* from the CPM (no cache snooping here :-).
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*
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* invalidate_dcache_range(unsigned long start, unsigned long stop)
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*/
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_GLOBAL(invalidate_dcache_range)
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li r5,L1_CACHE_BYTES-1
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andc r3,r3,r5
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subf r4,r3,r4
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add r4,r4,r5
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srwi. r4,r4,L1_CACHE_SHIFT
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beqlr
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mtctr r4
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1: dcbi 0,r3
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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sync /* wait for dcbi's to get to ram */
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blr
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/*
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* 40x cores have 8K or 16K dcache and 32 byte line size.
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* 44x has a 32K dcache and 32 byte line size.
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* 8xx has 1, 2, 4, 8K variants.
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* For now, cover the worst case of the 44x.
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* Must be called with external interrupts disabled.
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*/
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#define CACHE_NWAYS 64
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#define CACHE_NLINES 32
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_GLOBAL(flush_dcache)
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li r4,(2 * CACHE_NWAYS * CACHE_NLINES)
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mtctr r4
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lis r5,0
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1: lwz r3,0(r5) /* Load one word from every line */
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addi r5,r5,L1_CACHE_BYTES
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bdnz 1b
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sync
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blr
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_GLOBAL(invalidate_dcache)
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addi r6,0,0x0000 /* clear GPR 6 */
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/* Do loop for # of dcache congruence classes. */
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lis r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@ha /* TBS for large sized cache */
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ori r7,r7,(CONFIG_SYS_DCACHE_SIZE / L1_CACHE_BYTES / 2)@l
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/* NOTE: dccci invalidates both */
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mtctr r7 /* ways in the D cache */
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..dcloop:
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dccci 0,r6 /* invalidate line */
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addi r6,r6,L1_CACHE_BYTES /* bump to next line */
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bdnz ..dcloop
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sync
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blr
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/*
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* Cache functions.
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*
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* NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM,
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* although for some cache-ralated calls stubs have to be provided to satisfy
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* symbols resolution.
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* Icache-related functions are used in POST framework.
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*
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*/
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#ifdef CONFIG_440
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.globl dcache_disable
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.globl dcache_enable
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.globl icache_disable
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.globl icache_enable
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dcache_disable:
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dcache_enable:
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icache_disable:
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icache_enable:
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blr
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.globl dcache_status
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.globl icache_status
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dcache_status:
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icache_status:
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mr r3, 0
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blr
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#else /* CONFIG_440 */
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.globl icache_enable
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icache_enable:
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mflr r8
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bl invalidate_icache
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mtlr r8
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isync
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addis r3,r0, 0xc000 /* set bit 0 */
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mticcr r3
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blr
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.globl icache_disable
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icache_disable:
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addis r3,r0, 0x0000 /* clear bit 0 */
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mticcr r3
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isync
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blr
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.globl icache_status
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icache_status:
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mficcr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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.globl dcache_enable
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dcache_enable:
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mflr r8
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bl invalidate_dcache
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mtlr r8
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isync
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addis r3,r0, 0x8000 /* set bit 0 */
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mtdccr r3
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blr
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.globl dcache_disable
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dcache_disable:
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mflr r8
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bl flush_dcache
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mtlr r8
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addis r3,r0, 0x0000 /* clear bit 0 */
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mtdccr r3
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blr
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.globl dcache_status
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dcache_status:
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mfdccr r3
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srwi r3, r3, 31 /* >>31 => select bit 0 */
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blr
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#endif /* CONFIG_440 */
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